Intel Xeon User Manual

Design Guide 21
Introduction
1.3.2 Intel
®
E7500 Chipset
The E7500 chipset consists of three major components: the Intel
®
E7500 Memory Controller Hub
(referred to throughout this document as the MCH), the Intel
®
82801CA I/O Controller Hub 3-S
(hereafter referred to as ICH3-S), and the Intel
®
82870P2 PCI/ PCI-X 64-bit Hub 2 (abbreviated to
P64H2). The chipset components communicate via hub interfaces (HIs). The MCH provides four
hub interface connections: one for the ICH3-S and three for high-speed I/O using 82870P2 P64H2
components. The hub interfaces are point-to-point and therefore only support two agents (the MCH
plus one I/O device). Therefore, the system supports a total of three P64H2s.
1.3.2.1 Intel
®
E7500 Memory Controller Hub (MCH)
The MCH is a 1005-ball FC-BGA package and contains the following functionality:
• System Bus Features:
— Supports dual processors at 100 MHz (x4 transfers).
— System bus bandwidth of 3.2 GB/s (400 MHz).
— Supports 36-bit system bus addressing model.
— 12 deep in-order queue, 2 deep defer queue.
• Memory Bus Features:
— 144-bit wide, DDR-200 memory interface with memory bandwidth of 3.2 GB/s.
— Supports x72, ECC, registered DDR-200 DIMMs using 64-Mb, 128-Mb, 256-Mb and
512-Mb DRAMs.
— Supports a maximum of 16 GB of memory.
— Supports Single 4-bit Error Correct, Double 4-bit Error Detect (S4EC/D4ED) Chipkill
technology ECC (x4 Chipkill technology).
— Supports up to 32 simultaneous open pages.
• I/O Features:
— Provides HI1.5 connection for ICH3-S (Hub Interface A):
- 266 MB/s point-to-point connection for ICH3-S with parity protection.
- 8-bit wide, 66 MHz base clock, 4X data transfer.
- Parallel termination mode for longer trace lengths.
- 64-bit inbound addressing, 32-bit outbound addressing.
— Provides 3 HI2.0 Connections for P64H2s (Hub Interfaces B, C and D):
- 1.066 GB/s point-to-point connection for I/O bridges with ECC protection.
- 16-bit wide, 66 MHz base clock, 8X data transfer.
- Parallel termination mode for longer trace lengths.
- 64-bit inbound addressing, 32-bit outbound addressing.
• Power Management Features:
— Supports C0, C1, C2, S0, S1, S4, and S5 power states. (Does not support C3, C4, S2,
and S3).

Intel Xeon Specifications

General

Brand	Intel
Model	Xeon
Category	Processor
Language	English