Platform Clock Routing Guidelines
36 Design Guide
Table 4-2. Platform System Clock-Reference
Clock Group CK-408B Pin Component Component Pin Name
Host_CLK CPU# Debug Port BCLK[0]
CPU Debug Port BCLK[1]
CPU# Processor 0 BCLK[0]
CPU Processor 0 BCLK[1]
CPU# Processor 1 BCLK[0]
CPU Processor 1 BCLK[1]
CPU# MCH HCLKINP
CPU MCH HCLKINN
CLK66 66BUF MCH 66IN
ICH3-S CLK66
P64H2 CLK66
CLK33_ICH3-S PCIF ICH3-S PCICLK
CLK14 REF0 ICH3-S CLK14
SIO CLOCKl
CLK33 PCI PCI Connector #1 CLK
PCI Connector #2 CLK
PCI Connector #3 CLK
PCI Connector #4 CLK
PCI Connector #5 CLK
FWH CLK
SIO PCI_CLK
PCIF BMC LCLK
USBCLK USB-48MHZ ICH3-S CLK48
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