Intel Xeon User Manual

Design Guide 83
Hub Interface
Hub Interface 7
7.1 Signal Naming Convention
Figure 7-1 has the Hub Interface 2.0 and Hub Interface 1.5 signal naming convention for each
component. This figure is intended to give a quick naming cross reference to designers. The
specific guidelines and implementations on these signals are given in the following sections. Note
that throughout the document, the ‘x’ part of the MCH signal has been dropped for simplicity.
NOTES:
1. These signals have individual resistor dividers. For specific values, refer to Figure 7-5 and Figure 7-8.
2. These signals have individual pull-up resistors. For specific values, refer to Figure 7-6 and Figure 7-9.
3. Signal names for HI2.0 on the MCH: x = B, C, or D.
Figure 7-1. Signal Naming Convention on Both Sides of the Hub Interfaces
PUSTRBS
PUSTRBF
PSTRBS
PSTRBF
PUSTRBS_x
PUSTRBF_x
PSTRBS_x
PSTRBF_x
HI_[#]
HI[#]
HI2.0
HI_VSWING
1
HI_VREF
1
HI_RCOMP
2
HIRCOMP_x
2
HISWNG_x
1
HIVREF_x
1
HISWNG_A
1
HIVREF_A
1
HIRCOMP_A
2
HICOMP
2
HITERM
1
HIREF
1
HI_x[#]
HI_A[#]
HI_STBS
HI_STBF
HI_STBS
HI_STBF
HI1.5
MCH
Intel
®
P64H2
Intel
®
ICH3-S

Intel Xeon Specifications

General

Brand	Intel
Model	Xeon
Category	Processor
Language	English