Intel Xeon User Manual

Design Guide 3
Contents
1 Introduction................................................................................................................15
1.1 Reference Documentation...................................................................................15
1.2 Conventions and Terminology.............................................................................17
1.3 System Overview ................................................................................................19
1.3.1 Intel® Xeon™ Processor with 512 KB L2 Cache ...............................20
1.3.2 Intel® E7500 Chipset .........................................................................21
1.3.2.1 Intel® E7500 Memory Controller Hub (MCH) .......................21
1.3.2.2 I/O Controller Hub 3 (Intel
®
ICH3-S).....................................22
1.3.2.3 PCI/PCI-X 64-bit Hub 2 (Intel
®
82870P2 P64H2).................22
1.3.3 Bandwidth Summary ..........................................................................23
1.3.4 System Configurations .......................................................................23
2 Component Quadrant Layout..............................................................................25
2.1 Intel® Xeon™ Processor with 512 KB L2 Cache Quadrant Layout ....................26
2.2 Intel® E7500 MCH Quadrant Layout...................................................................27
2.3 Intel
®
ICH3-S Quadrant Layout...........................................................................28
2.4 Intel
®
82870P2 P64H2 Quadrant Layout ............................................................29
3 Platform Stack-Up and Component Placement Overview.......................31
3.1 Platform Component Placement .........................................................................31
3.2 Platform Stack-Up ...............................................................................................32
4 Platform Clock Routing Guidelines..................................................................35
4.1 Clock Groups.......................................................................................................38
4.1.1 HOST_CLK Clock Group ...................................................................38
4.1.1.1 HOST_CLK Clock Topology.................................................38
4.1.1.2 HOST_CLK General Routing Guidelines..............................41
4.1.1.3 CK408 vs. CK408B Requirement .........................................41
4.1.2 CLK66 Clock Group ...........................................................................42
4.1.2.1 CLK66 Skew Requirements..................................................43
4.1.3 CLK33_ICH3-S Clock.........................................................................45
4.1.4 CLK33 Clock Group ...........................................................................46
4.1.5 CLK14 Clock Group ...........................................................................48
4.1.6 USBCLK Clock Group ........................................................................49
4.2 Clock Driver Decoupling......................................................................................50
4.3 Clock Driver Power Delivery................................................................................51
4.4 EMI Constraints...................................................................................................51
5 System Bus Routing Guidelines........................................................................53
5.1 Routing Guidelines for the AGTL+ Source Synchronous 2X and 4X Groups .....56
5.1.1 Trace Length Matching.......................................................................56
5.2 Routing Guidelines for Common Clock Signals ..................................................58
5.2.1 Wired-OR Signals...............................................................................58
5.2.2 RESET# Topology..............................................................................59
5.3 Routing Guidelines for Asynchronous GTL+ and Miscellaneous Signals ...........59
5.3.1 Asynchronous GTL+ Signals Driven by the Processor ......................60
5.3.1.1 Proper THERMTRIP# Usage................................................61

Intel Xeon Specifications

General

Brand	Intel
Model	Xeon
Category	Processor
Language	English