Intel Xeon - Page 4

4 Design Guide
5.3.2 Asynchronous GTL+ Signals Driven by the Chipset ..........................61
5.3.2.1 Proper Power Good Usage ..................................................62
5.3.2.2 Voltage Translation for INIT#................................................62
5.3.3 VID[4:0] ..............................................................................................63
5.3.4 SMBus Signals...................................................................................63
5.3.5 System Bus COMP Routing Guidelines.............................................64
5.3.6 BR[3:0]# Routing Guidelines..............................................................64
5.3.7 ODTEN Signal Routing Guidelines ....................................................64
5.3.8 TESTHI[6:0] Routing Guidelines ........................................................65
5.3.9 SKTOCC# Signal Routing Guidelines................................................65
6 Memory Interface Routing Guidelines.............................................................67
6.1 DDR Overview ....................................................................................................68
6.2 Source Synchronous Signal Group.....................................................................70
6.3 Command Clock Routing ....................................................................................73
6.4 Source Clocked Signal Group Routing ...............................................................75
6.5 Chip Select Routing ............................................................................................76
6.6 Clock Enable Routing..........................................................................................77
6.7 Enable Signal (RCVEN#) ....................................................................................78
6.8 Miscellaneous Signals.........................................................................................79
6.9 DDR Reference Voltage......................................................................................80
6.10 DDR Signal Termination .....................................................................................81
6.11 Decoupling Requirements...................................................................................82
7 Hub Interface..............................................................................................................83
7.1 Signal Naming Convention..................................................................................83
7.2 Hub Interface 2.0 Implementation.......................................................................84
7.2.1 Hub Interface 2.0 High-Speed Routing Guidelines ............................84
7.2.2 Hub Interface 2.0 Generation/Distribution of Reference Voltages .....87
7.2.3 Hub Interface 2.0 Resistive Compensation........................................88
7.2.4 Hub Interface 2.0 Decoupling Guidelines...........................................89
7.2.5 Unused Hub Interface 2.0 Interfaces..................................................89
7.3 Hub Interface 1.5 Implementation.......................................................................89
7.3.1 Hub Interface 1.5 High-Speed Routing Guidelines ............................89
7.3.2 Hub Interface 1.5 Generation/Distribution of Reference Voltages .....90
7.3.3 Hub Interface 1.5 Resistive Compensation........................................91
7.3.4 Hub Interface 1.5 Decoupling Guidelines...........................................92
8Intel
®
82870P2 (P64H2)..........................................................................................93
8.1 PCI/PCI-X Design Guidelines .............................................................................93
8.1.1 PCI/PCI-X Routing Requirements (No Hot Plug) ...............................94
8.1.2 PCI/PCI-X Hot Plug Routing Requirements .......................................95
8.1.3 Clock Configuration............................................................................96
8.1.4 Loop Clock Configuration...................................................................97
8.1.5 IDSEL Implementation .......................................................................98
8.1.6 SMBus Address..................................................................................98
8.2 Hot Plug Implementation.....................................................................................99
8.2.1 Standard Usage Model.......................................................................99
8.2.1.1 Hot-Removals.......................................................................99
8.2.1.2 Hot-Insertions .....................................................................100
8.2.2 Hot Plug Switch Implementation ......................................................100