Design Guide 5
8.2.2.1 Manually-Operated Retention Latch Sensor.......................101
8.2.2.2 Optional Attention Button....................................................102
8.2.3 LED Indicator Outputs......................................................................102
8.2.4 Disabling/Enabling an Intel
®
P64H2 Hot Plug Controller..................103
8.2.4.1 Hot Plug Strapping Options ................................................103
8.2.4.2 Hot Plug Registers’ Visibility...............................................103
8.2.5 Single Slot Parallel Mode .................................................................103
8.2.5.1 Required Additional Logic...................................................103
8.2.5.2 PCI Clock............................................................................103
8.2.5.3 Debounced Hot Plug Switch Input......................................104
8.2.5.4 Comparator Circuit for PCIXCAP1/PCIXCAP2 Pins...........104
8.2.5.5 Tri-State Buffer or 2:1 MUX for HPxSLOT [2:0]..................104
8.2.5.6 Hot Plug Muxed Signals in Single Slot Parallel Mode ........105
8.2.5.7 SMBus Address Considerations.........................................106
8.2.5.8 Pull-Ups/Pull-Downs in Single Slot Parallel Mode..............106
8.2.5.9 Reference Schematic for Single-Slot Parallel Mode...........107
8.2.6 Dual Slot Parallel Mode....................................................................108
8.2.6.1 Required Additional Logic...................................................108
8.2.6.2 Debounced Hot Plug Switch Input......................................108
8.2.6.3 Comparator Circuit for PCIXCAP1/PCIXCAP2 Pins...........108
8.2.6.4 Tri-State Buffer or 2:1 Mux for HPxSLOT [2:0]...................108
8.2.6.5 HPx_SID Output Signal ......................................................108
8.2.6.6 Pull-Ups/Pull-Downs in Dual Slot Parallel Mode.................108
8.2.6.7 Hot Plug Muxed Signals in Dual Slot Parallel Mode...........109
8.2.6.8 SMBus Address Considerations.........................................110
8.2.6.9 Reference Schematic for Dual-Slot Parallel Mode .............111
8.2.7 Three or More Slot Serial Mode .......................................................112
8.2.7.1 Hot Plug and Non-Hot Plug Combinations .........................112
8.2.7.2 Required Additional Logic...................................................112
8.2.7.3 Debounced Hot Plug Switch Input......................................112
8.2.7.4 Comparator Circuit for PCIXCAP1/PCIXCAP2 Pins...........112
8.2.7.5 HPxSLOT [2:0]....................................................................112
8.2.7.6 Stutter Logic for Implementing Fewer Than Six Slots.........112
8.2.7.7 Pull-Ups/Pull-Downs in Three or More Slot Serial Mode....113
8.2.7.8 Reference Schematic for Serial Mode................................114
8.2.8 Intel
®
P64H2 PCI Interface PCIXCAP and M66EN Pins..................115
8.2.8.1 PCIXCAP Pin Requirements ..............................................115
8.2.8.2 M66EN Pin Requirements ..................................................115
9 I/O Controller Hub..................................................................................................119
9.1 IDE Interface .....................................................................................................119
9.1.1 Cabling .............................................................................................119
9.1.2 Cable Detection for Ultra ATA/66 and Ultra ATA/100 ......................120
9.1.2.1 Combination Host-Side/Device-Side Cable Detection........120
9.1.3 Primary IDE Connector Requirements .............................................121
9.1.4 Secondary IDE Connector Requirements ........................................122
9.2 SPKR Pin Consideration ...................................................................................123
9.3 PCI ....................................................................................................................123
9.4 USB...................................................................................................................124
9.4.1 General Routing and Placement ......................................................124
9.4.2 USB Trace Separation .....................................................................125
9.4.3 USB Trace Length Matching ............................................................125