Design Guide 35
Platform Clock Routing Guidelines
Platform Clock Routing Guidelines 4
To minimize jitter, improve routing, and reduce cost, E7500 chipset-based systems should use a
single chip clock solution, the CK408B. In this configuration, the CK408B provides four, 100 MHz
differential outputs pairs for all of the bus agents, including the ITP connector, and five, 66 MHz
speed clocks that drive all I/O buses. Figure 4-1 shows the implementation of the bus clocks for
this configuration.
For more information on CK408B compliance, refer to the CK408B Clock Synthesizer
Specification Specifically for E7500 Chipset DP with ITP System Clock Generator Document.
Table 4-1. CK408B Clock Groups
Clock Group
Name
Frequency
(MHz)
Receiver
Host_CLK 100 Processor 0, Processor 1, Debug Port and MCH
CLK66 66 MCH, ICH3-S, and P64H2
CLK33_ICH3-S 33 ICH3-S
CLK14 14.318 ICH3-S and SIO
CLK33 33 PCI Connector, SIO, BMC, and FWH
USBCLK 48 ICH3-S
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