Intel Xeon User Manual

Design Guide 15
Introduction
Introduction 1
The Intel
®
Xeon™ Processor with 512 KB L2 Cache and Intel
®
E7500 Chipset Platform Design
Guide documents Intel’s design recommendations for systems based on the Intel
®
Xeon™
Processor with 512 KB L2 Cache and the E7500 chipset. In addition to providing motherboard
design recommendations such as layout and routing guidelines, this document addresses system
design issues such as power delivery.
Carefully follow the design information, board schematics, debug recommendations, and system
checklists provided in this document. These design guidelines have been developed to ensure
maximum flexibility for board designers while reducing the risk of board related issues.
Note that the guidelines recommended in this document are based on experience and simulation
work done at Intel while developing Intel Xeon processor with 512 KB L2 cache / E7500 chipset-
based systems. This work is ongoing, and the recommendations are subject to change.
Board designers may use the associated Intel schematics as a reference. While the schematics cover
a specific design implementation, the core schematics remain the same for most E7500 chipset-
based platforms. The schematic set provides a reference schematic for each E7500 chipset
component as well as common motherboard options. Additional flexibility is possible through
other permutations of these options and components.
1.1 Reference Documentation
Note: For the latest revision and documentation number, contact your appropriate field representative.
Table 1-1. Reference Documents
Document
Document
Number/Source
603-Pin Socket Design Guidelines
http://developer.intel.com/design/
Xeon/guides/249672.htm
82562ET 10/100 Mbps Platform LAN Connect (PLC) Product Datasheet
APIC External Design Specification
AT Attachment - 6 with packet Interface (ATA/ATAPI - 6)
CK-408B Clock Synthesizer/Driver Specification Revision 1.1
ITP700 Debug Port Design Guide
http://developer.intel.com/design/
Xeon/guides/
Intel
®
Xeon™ Processor with 512 KB L2 Cache Signal Integrity Models
http://developer.intel.com/design/
Xeon/devtools
Intel
®
82801CA I/O Controller Hub 3 (ICH3-S) Datasheet 290733
Intel
®
PCI-64 Hub 2 (P64H2) Thermal and Mechanical Design Guidelines 298648
Intel
®
E7500 Chipset Thermal and Mechanical Design Guidelines 298647
Intel
®
PCI-64 Hub 2 (P64H2) Datasheet 290732
Intel
®
E7500 Chipset Memory Controller Hub (MCH) Datasheet 290730

Intel Xeon Specifications

General

Brand	Intel
Model	Xeon
Category	Processor
Language	English