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Intel Xeon E5-2600 Series - User Manual
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Reference Numbe
r: 327043-001
Intel® Xeon® Processor E5-2600
Product Family Uncore Performance
Monitoring Guide
March 2012
2
Table of Contents
Main Page
Default Chapter
3
Table of Contents
3
1 Introduction
9
Uncore PMON Overview
9
Uncore Sub-System Block Diagram of Intel Xeon Processor E5-2600 Family
9
Section References
10
Per-Box Performance Monitoring Capabilities
10
Uncore PMON - Typical Control/Counter Logic
11
Perfmon Control/Counter Block Diagram
11
Uncore PMU Summary Tables
12
MSR Space Uncore Performance Monitoring Registers
12
PCICFG Space Uncore Performance Monitoring Registers
13
On Parsing and Using Derived Events
14
On Common Terms Found in Derived Events
15
2 Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring
17
Uncore Per-Socket Performance Monitoring Control
17
Setting up a Monitoring Session
17
Reading the Sample Interval
18
Ubox Performance Monitoring
19
Overview of the Ubox
19
Ubox Performance Monitoring Overview
19
Ubox Performance Monitors
19
Ubox Box Level PMON State
19
Ubox Performance Monitoring Msrs
19
Ubox PMON State - Counter/Control Pairs
20
U_MSR_PMON_CTL{1-0} Register - Field Definitions
20
U_MSR_PMON_CTR{1-0} Register - Field Definitions
20
Ubox Performance Monitoring Events
21
UBOX Box Events Ordered by Code
21
UBOX Box Performance Monitor Event List
21
U_MSR_PMON_FIXED_CTL Register - Field Definitions
21
U_MSR_PMON_FIXED_CTR Register - Field Definitions
21
Caching Agent (Cbo) Performance Monitoring
22
Overview of the Cbo
22
Cbo Performance Monitoring Overview
23
Special Note on Cbo Occupancy Events
23
Cbo Performance Monitors
24
Cbo Performance Monitoring Msrs
24
Cbo Box Level PMON State
27
Cbo PMON State - Counter/Control Pairs
27
Cn_Msr_Pmon_Box_Ctl Register - Field Definitions
27
Cbo Filter Register (Cn_Msr_Pmon_Box_Filter)
28
Cn_Msr_Pmon_Ctr{3-0} Register - Field Definitions
28
Cn_Msr_Pmon_Box_Filter Register - Field Definitions
29
Cbo Performance Monitoring Events
30
Acronyms Frequently Used in Cbo Events
30
An Overview
30
Cbo Events Ordered by Code
31
The Queues
31
CBO Box Common Metrics (Derived Events)
32
Cbo Performance Monitor Event List
34
Home Agent (HA) Performance Monitoring
45
Overview of the Home Agent
45
HA Box Level PMON State
46
HA Performance Monitoring Overview
46
HA Performance Monitors
46
HA Performance Monitoring Msrs
46
HA PMON State - Counter/Control Pairs
47
HA_PCI_PMON_BOX_CTL Register - Field Definitions
47
HA_PCI_PMON_CTR{3-0} Register - Field Definitions
48
HA_PCI_PMON_BOX_OPCODEMATCH Register - Field Definitions
48
HA_PCI_PMON_BOX_ADDRMATCH1 Register - Field Definitions
48
HA Performance Monitoring Events
49
On the Major HA Structures
49
HA_PCI_PMON_BOX_ADDRMATCH0 Register - Field Definitions
49
HA Box Events Ordered by Code
50
HA Box Common Metrics (Derived Events)
50
HA Box Performance Monitor Event List
51
Memory Controller (IMC) Performance Monitoring
59
Functional Overview
59
IMC Performance Monitoring Overview
59
Overview of the IMC
59
IMC Performance Monitors
60
MC Box Level PMON State
60
IMC Performance Monitoring Msrs
60
Mc_Chy_Pci_Pmon_Box_Ctl Register - Field Definitions
60
MC PMON State - Counter/Control Pairs
61
Mc_Chy_Pci_Pmon_Ctl{3-0} Register - Field Definitions
61
IMC Performance Monitoring Events
62
An Overview
62
Mc_Chy_Pci_Pmon_Fixed_Ctl Register - Field Definitions
62
Mc_Chy_Pci_Pmon_Ctr{Fixed,3-0} Register - Field Definitions
62
IMC Box Events Ordered by Code
63
IMC Box Common Metrics (Derived Events)
63
IMC Box Performance Monitor Event List
64
Power Control (PCU) Performance Monitoring
72
Overview of the PCU
72
PCU Performance Monitoring Overview
72
PCU Performance Monitors
72
PCU Performance Monitoring Msrs
72
PCU Box Level PMON State
73
PCU_MSR_PMON_BOX_CTL Register - Field Definitions
73
PCU PMON State - Counter/Control Pairs
74
PCU_MSR_PMON_CTL{3-0} Register - Field Definitions
74
PCU_MSR_PMON_CTR{3-0} Register - Field Definitions
75
Intel® PCU Extra Registers - Companions to PMON HW
76
PCU Performance Monitoring Events
76
An Overview
76
PCU_MSR_PMON_BOX_FILTER Register - Field Definitions
76
PCU_MSR_CORE_C6_CTR Register - Field Definitions
76
PCU_MSR_CORE_C3_CTR Register - Field Definitions
76
PCU Box Events Ordered by Code
78
PCU Box Common Metrics (Derived Events)
79
PCU Box Performance Monitor Event List
79
Intel® QPI Link Layer Performance Monitoring
87
Overview of the Intel® QPI Box
87
Intel® QPI Performance Monitoring Overview
87
Intel® QPI Performance Monitors
88
Intel® QPI Box Level PMON State
88
Intel® QPI Performance Monitoring Registers
88
Intel® QPI PMON State - Counter/Control Pairs
89
Q_Py_Pci_Pmon_Box_Ctl Register - Field Definitions
89
Q_Py_Pci_Pmon_Ctl{3-0} Register - Field Definitions
89
Intel® QPI Registers for Packet Mask/Match Facility
90
Q_Py_Pci_Pmon_Ctr{3-0} Register - Field Definitions
90
Q_Py_Pci_Pmon_Pkt_Match1 Registers
91
Q_Py_Pci_Pmon_Pkt_Match0 Registers
91
Q_Py_Pci_Pmon_Pkt_Mask1 Registers
92
Q_Py_Pci_Pmon_Pkt_Mask0 Registers
92
Intel® QPI Extra Registers - Companions to PMON HW
94
Intel® QPI LL Performance Monitoring Events
94
An Overview
94
Acronyms Frequently Used in Intel® QPI Events
95
Intel® QPI LL Box Events Ordered by Code
95
Intel QPI LL Box Common Metrics (Derived Events)
96
Intel® QPI LL Box Performance Monitor Event List
98
R2Pcie Performance Monitoring
111
Overview of the R2Pcie Box
111
R2Pcie Performance Monitoring Overview
111
R2Pcie Performance Monitors
112
R2Pcie Box Level PMON State
112
R2Pcie Performance Monitoring Registers
112
R2_PCI_PMON_BOX_CTL Register - Field Definitions
112
R2Pcie PMON State - Counter/Control Pairs
113
R2Pcie Performance Monitoring Events
114
An Overview
114
R2Pcie Box Events Ordered by Code
114
R2Pcie Box Common Metrics (Derived Events)
114
R2Pcie Box Performance Monitor Event List
115
R3QPI Performance Monitoring
119
Overview of the R3QPI Box
119
R3QPI Performance Monitoring Overview
119
R3QPI Performance Monitors
120
R3QPI Box Level PMON State
120
R3QPI Performance Monitoring Registers
120
R3_Ly_Pci_Pmon_Box_Ctl Register - Field Definitions
120
R3QPI PMON State - Counter/Control Pairs
121
R3_Ly_Pci_Pmon_Ctl{2-0} Register - Field Definitions
121
R3_Ly_Pci_Pmon_Ctr{2-0} Register - Field Definitions
121
R3QPI Performance Monitoring Events
122
An Overview
122
R3QPI Box Events Ordered by Code
122
R3QPI Box Common Metrics (Derived Events)
123
R3QPI Box Performance Monitor Event List
123
Packet Matching Reference
131
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Intel Xeon E5-2600 Series Specifications
General
Brand
Intel
Model
Xeon E5-2600 Series
Category
Computer Hardware
Language
English
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