Intel Xeon E5-2600 Series - Ubox Performance Monitoring Events; UBOX Box Events Ordered by Code; UBOX Box Performance Monitor Event List; U_MSR_PMON_FIXED_CTL Register - Field Definitions

Reference Number: 327043-001 21
Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring
2.2.4 UBox Performance Monitoring Events
The set of events that can be monitored in the UBox are summarized in Section 2.2.
2.2.5 UBOX Box Events Ordered By Code
The following table summarizes the directly measured UBOX Box events.
2.2.6 UBOX Box Performance Monitor Event List
The section enumerates the uncore performance monitoring events for the UBOX Box.
EVENT_MSG
• Title: VLW Received
• Category: EVENT_MSG Events
• Event Code: 0x42
• Max. Inc/Cyc: 1, Register Restrictions: 0-1
• Definition: Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread
to filter on using NCUPMONCTRLGLCTR.ThreadID.
Table 2-4. U_MSR_PMON_FIXED_CTL Register – Field Definitions
Field Bits Attr
HW
Rese
t Val
Description
rsv 31:23 RV 0 Reserved (?)
en 22 RW 0 Enable counter when global enable is set.
rsv 21:20 RV 0 Reserved. SW must write to 0 for proper operation.
rsv 19:0 RV 0 Reserved (?)
Table 2-5. U_MSR_PMON_FIXED_CTR Register – Field Definitions
Field Bits Attr
HW
Reset
Val
Description
rsv 63:44 RV 0 Reserved (?)
event_count 43:0 RW-V 0 48-bit performance event counter
Table 2-6. Performance Monitor Events for UBOX
Symbol Name
Event
Code
Extra
Select
Bit
Ctrs
Max
Inc/
Cyc
Description
EVENT_MSG 0x42 0 0-1 1 VLW Received
LOCK_CYCLES 0x44 0 0-1 1 IDI Lock/SplitLock Cycles