Intel Xeon E5-2600 Series - Intel PCU Extra Registers - Companions to PMON HW; PCU Performance Monitoring Events; An Overview; PCU_MSR_PMON_BOX_FILTER Register - Field Definitions

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring
76 Reference Number: 327043-001
• For frequency/voltage band filters, the multipler is at 100MHz granularity. So, a value of 32
(0x20) would represent a frequency of 3.2GHz.
• Support for limited Frequency/Voltage Band histogramming. Each of the four bands provided for
in the filter may be simultaneous tracked by the corresonding event
Note: Since use of the register as a filter is heavily overloaded, simultaneous application of
this filter to additional events in the same run is severely limited
2.6.3.3 Intel® PCU Extra Registers - Companions to PMON HW
The PCU includes two extra MSRs that track the number of cycles a core (any core) is in either the C3
or C6 state. As mentioned before, these counters are not part of the PMON infrastructure so they
can’t be frozen or reset with the otherwise controlled by the PCU PMON control registers.
Note: To be clear, these counters track the number of cycles some core is in C3/6 state. It
does not track the total number of cores in the C3/6 state in any cycle. For that, a user
should refer to the regular PCU event list.
2.6.4 PCU Performance Monitoring Events
2.6.4.1 An Overview:
The PCU provides the ability to capture information covering a wide range of the PCU’s functionality
including:
• Number of cores in a given C-state per-cycle
Table 2-77. PCU_MSR_PMON_BOX_FILTER Register – Field Definitions
Field Bits Attr
HW
Reset
Val
Description
rsv 63:48 RV 0 Reserved (?)
filt31_24 31:24 RW-V 0 Band 3 - For Voltage/Frequency Band Event
filt23_16 23:16 RW-V 0 Band 2 - For Voltage/Frequency Band Event
filt15_8 15:8 RW-V 0 Band 1 - For Voltage/Frequency Band Event
filt7_0 7:0 RW-V 0 Band 0 - For Voltage/Frequency Band Event
Table 2-78. PCU_MSR_CORE_C6_CTR Register – Field Definitions
Field Bits Attr
HW
Reset
Val
Description
event_count 63:0 RW-V 0 64-bit performance event counter
Table 2-79. PCU_MSR_CORE_C3_CTR Register – Field Definitions
Field Bits Attr
HW
Reset
Val
Description
event_count 63:0 RW-V 0 64-bit performance event counter