Intel Xeon E5-2600 Series - Memory Controller (IMC) Performance Monitoring; Functional Overview; IMC Performance Monitoring Overview; Overview of the IMC

Reference Number: 327043-001 59
Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring
2.5 Memory Controller (iMC) Performance Monitoring
2.5.1 Overview of the iMC
The integrated Memory Controller provides the interface to DRAM and communicates to the rest of
the uncore through the Home Agent (i.e. the iMC does not connect to the Ring).
In conjunction with the HA, the memory controller also provides a variety of RAS features, such as
ECC, lockstep, memory access retry, memory scrubbing, thermal throttling, mirroring, and rank
sparing.
2.5.2 Functional Overview
The memory controller is the interface between the home Home Agent (HA) and DRAM, translating
read and write commands into specific memory commands and schedules them with respect to
memory timing. The other main function of the memory controller is advanced ECC support.
Because of the data path affinity to the HA data path, the HA is paired with the memory controller.
The Intel Xeon Processor E5-2600 supports four channels of DDR3 or metaRAM. For DDR3, the
number of DIMMs per channel depends on the speed it is running and the package.
• Support for unbuffered DDR3 and registered DDR3
• Up to four independent DDR3 channels
• Eight independent banks per rank
• Support for DDR3 frequencies of 800,1067, 1333, 1600 GT/s. The speed achievable is
dependent on the number of DIMMs per channel.
• Up to three DIMMs per channel (depends on the speed)
• Support for x4, x8 and x16 data lines per native DDR3 device
• ECC support (correct any error within a x4 device)
• Lockstep support for x8 chipfail
• Open or closed page policy
• Channel Mirroring per socket
• Demand and Patrol Scrubbing support
• Memory Initialization
• Poisoning Support
• Support for LR-DIMMs (load reduced) for a buffered memory solution demanding higher capacity
memory subsytems.
• Support for low voltage DDR3 (LV-DDR3, 1.35V)
2.5.3 iMC Performance Monitoring Overview
The iMC supports event monitoring through four 48-bit wide counters
(MC_CHy_PCI_PMON_CTR{3:0}) and one fixed counter (MC_CHy_PCI_PMON_FIXED_CTR) for each
DRAM channel (of which there are 4 in Intel Xeon Processor E5-2600 family) the MC is attached to.
Each of these counters can be programmed (MC_CHy_PCI_PMON_CTL{3:0}) to capture any MC
event. The MC counters will increment by a maximum of 8b per cycle.