Intel Xeon E5-2600 Series - HA PMON State - Counter;Control Pairs; HA_PCI_PMON_BOX_CTL Register - Field Definitions

Reference Number: 327043-001 47
Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring
In the case of the HA, the HA_PCI_PMON_BOX_CTL register governs what happens when a freeze
signal is received (.frz_en). It also provides the ability to manually freeze the counters in the box
(.frz).
2.4.3.2 HA PMON state - Counter/Control Pairs
The following table defines the layout of the HA performance monitor control registers. The main task
of these configuration registers is to select the event to be monitored by their respective data counter
(.ev_sel, .umask). Additional control bits are provided to shape the incoming events (e.g. .invert,
.edge_det, .thresh).
Table 2-34. HA_PCI_PMON_BOX_CTL Register – Field Definitions
Field Bits Attr
HW
Reset
Val
Description
rsv 31:18 RV 0 Reserved (?)
rsv 17 RV 0 Reserved; SW must write to 0 else behavior is undefined.
frz_en 16 WO 0 Freeze Enable.
If set to 1 and a freeze signal is received, the counters will be
stopped or ‘frozen’, else the freeze signal will be ignored.
rsv 15:9 RV 0 Reserved (?)
frz 8 WO 0 Freeze.
If set to 1 and the .frz_en is 1, the counters in this box will be
frozen.
rsv 7:2 RV 0 Reserved (?)
rsv 1:0 RV 0 Reserved; SW must write to 0 else behavior is undefined.
Table 2-35. HA_PCI_PMON_CTL{3-0} Register – Field Definitions (Sheet 1 of 2)
Field Bits Attr
HW
Reset
Val
Description
thresh 31:24 RW-V 0 Threshold used in counter comparison.
invert 23 RW-V 0 Invert comparison against Threshold.
0 - comparison will be ‘is event increment >= threshold?’.
1 - comparison is inverted - ‘is event increment < threshold?’
NOTE: .invert is in series following .thresh, Due to this, the
.thresh field must be set to a non-0 value. For events that
increment by no more than 1 per cycle, set .thresh to 0x1.
Also, if .edge_det is set to 1, the counter will increment when a 1
to 0 transition (i.e. falling edge) is detected.
en 22 RW-V 0 Local Counter Enable.
rsv 21:20 RV 0 Reserved. SW must write to 0 else behavior is undefined.
rsv 19 RV 0 Reserved (?)
edge_det 18 RW-V 0 When set to 1, rather than measuring the event in each cycle it
is active, the corresponding counter will increment when a 0 to 1
transition (i.e. rising edge) is detected.
When 0, the counter will increment in each cycle that the event
is asserted.
NOTE: .edge_det is in series following .thresh, Due to this, the
.thresh field must be set to a non-0 value. For events that
increment by no more than 1 per cycle, set .thresh to 0x1.