Intel Xeon E5-2600 Series - R2 Pcie Performance Monitors; R2 Pcie Box Level PMON State; R2 Pcie Performance Monitoring Registers; R2_PCI_PMON_BOX_CTL Register - Field Definitions

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring
112 Reference Number: 327043-001
2.8.3 R2PCIe Performance Monitors
2.8.3.1 R2PCIe Box Level PMON State
The following registers represent the state governing all box-level PMUs in the R2PCIe Box.
In the case of the R2PCIe, the R2_PCI_PMON_BOX_CTL register governs what happens when a
freeze signal is received (.frz_en). It also provides the ability to manually freeze the counters in the
box (.frz) and reset the generic state (.rst_ctrs and .rst_ctrl).
Table 2-104.R2PCIe Performance Monitoring Registers
Register Name
PCICFG
Address
Size
(bits)
Description
PCICFG Base Address Dev:Func
R2PCIe PMON Registers D19:F1
Box-Level Control/Status
R2_PCI_PMON_BOX_CTL F4 32 R2PCIe PMON Box-Wide Control
Generic Counter Control
R2_PCI_PMON_CTL3 E4 32 R2PCIe PMON Control for Counter 3
R2_PCI_PMON_CTL2 E0 32 R2PCIe PMON Control for Counter 2
R2_PCI_PMON_CTL1 DC 32 R2PCIe PMON Control for Counter 1
R2_PCI_PMON_CTL0 D8 32 R2PCIe PMON Control for Counter 0
Generic Counters
R2_PCI_PMON_CTR3 BC+B8 32x2 R2PCIe PMON Counter 3
R2_PCI_PMON_CTR2 B4+B0 32x2 R2PCIe PMON Counter 2
R2_PCI_PMON_CTR1 AC+A8 32x2 R2PCIe PMON Counter 1
R2_PCI_PMON_CTR0 A4+A0 32x2 R2PCIe PMON Counter 0
Table 2-105.R2_PCI_PMON_BOX_CTL Register – Field Definitions
Field Bits Attr
HW
Reset
Val
Description
rsv 31:18 RV 0 Reserved (?)
rsv 17 RV 0 Reserved; SW must write to 0 else behavior is undefined.
frz_en 16 WO 0 Freeze Enable.
If set to 1 and a freeze signal is received, the counters will be
stopped or ‘frozen’, else the freeze signal will be ignored.
rsv 15:9 RV 0 Reserved (?)
frz 8 WO 0 Freeze.
If set to 1 and the .frz_en is 1, the counters in this box will be
frozen.
rsv 7:2 RV 0 Reserved (?)
rst_ctrs 1 WO 0 Reset Counters.
When set to 1, the Counter Registers will be reset to 0.
rst_ctrl 0 WO 0 Reset Control.
When set to 1, the Counter Control Registers will be reset to 0.