Intel Xeon E5-2600 Series - Intel QPI Performance Monitors; Intel QPI Box Level PMON State; Intel QPI Performance Monitoring Registers

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring
88 Reference Number: 327043-001
2.7.3 Intel® QPI Performance Monitors
2.7.3.1 Intel® QPI Box Level PMON State
The following registers represent the state governing all box-level PMUs in each Port of the Intel® QPI
Box.
In the case of the Intel® QPI Ports, the Q_Py_PCI_PMON_BOX_CTL register governs what happens
when a freeze signal is received (.frz_en). It also provides the ability to manually freeze the counters
in the box (.frz) and reset the generic state (.rst_ctrs and .rst_ctrl).
Table 2-84. Intel® QPI Performance Monitoring Registers
Register Name
PCICFG
Address
Size
(bits)
Description
PCICFG Base Address Dev:Func
QPI Port 0 PMON Registers D8:F2
QPI Port 1 PMON Registers D9:F2
Box-Level Control/Status
Q_Py_PCI_PMON_BOX_CTL F4 32 QPI Port y PMON Box-Wide Control
Generic Counter Control
Q_Py_PCI_PMON_CTL3 E4 32 QPI Port y PMON Control for Counter 3
Q_Py_PCI_PMON_CTL2 E0 32 QPI Port y PMON Control for Counter 2
Q_Py_PCI_PMON_CTL1 DC 32 QPI Port y PMON Control for Counter 1
Q_Py_PCI_PMON_CTL0 D8 32 QPI Port y PMON Control for Counter 0
Generic Counters
Q_Py_PCI_PMON_CTR3 BC+B8 32x2 QPI Port y PMON Counter 3
Q_Py_PCI_PMON_CTR2 B4+B0 32x2 QPI Port y PMON Counter 2
Q_Py_PCI_PMON_CTR1 AC+A8 32x2 QPI Port y PMON Counter 1
Q_Py_PCI_PMON_CTR0 A4+A0 32x2 QPI Port y PMON Counter 0
QPI Mask/Match Port 0 PMON Registers D8:F6
QPI Mask/Match Port 1 PMON Registers D9:F6
Box-Level Filters
Q_Py_PCI_PMON_PKT_MASK1 23C 32 QPI Port y PMON Packet Filter Mask 1
Q_Py_PCI_PMON_PKT_MASK0 238 32 QPI Port y PMON Packet Filter Mask 0
Q_Py_PCI_PMON_PKT_MATCH1 22C 32 QPI Port y PMON Packet Filter Match 1
Q_Py_PCI_PMON_PKT_MATCH0 228 32 QPI Port y PMON Packet Filter Mask 0
QPI Misc Register Port 0 D8:F0
QPI Misc Register Port 1 D9:F1
Misc (Non-PMON) Counters
QPI_RATE_STATUS 0xD4 32 QPI Rate Status