Intel Xeon E5-2600 Series - Reading the Sample Interval

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring
18 Reference Number: 327043-001
Program the .ev_sel and .umask bits in the control register with the encodings necessary to capture
the requested event along with any signal conditioning bits (.thresh/.edge_det/.invert) used to qualify
the event.
e.g., Set C0_MSR_PMON_CT2.{ev_sel, umask} to {0x03, 0x1} in order to capture
LLC_VICTIMS.M_STATE in CBo 0’s C0_MSR_PMON_CTR2.
Note: It is also important to program any additional filter registers used to further qualify the
events (e.g., setting the opcode match field in Cn_MSR_BOX_FILTER to qualify
TOR_INSERTS by a specific opcode).
Back to the box level:
e) Reset counters in each box to ensure no stale values have been acquired from previous sessions.
• For each CBo, set Cn_MSR_PMON_BOX_CTL[1:0] to 0x2.
• For each Intel® QPI Port, set Q_Py_PCI_PMON_BOX_CTL[1:0] to 0x2.
• Set PCU_MSR_PMON_BOX_CTL[1:0] to 0x2.
• For each Link, set R3QPI_PCI_PMON_BOX_CTL[1:0] to 0x2.
• Set R2PCIE_PCI_PMON_BOX_CTL[1:0] to 0x2.
Note: The UBox does not have a Unit Control register and neither the iMC nor the HA have a
reset bit in their Unit Control register. The counters in the UBox, the HA each populated
DRAM channel in the iMC will need to be manually reset by writing a 0 in each data
register.
Back to the box level:
f) Commence counting at the box level by unfreezing the counters in each box
e.g., set Cn_MSR_PMON_BOX_CTL.frz to 0
And with that, counting will begin.
Note: The UBox does not have a Unit Control register. Once enabled and programmed with a
valid event, they will be collecting events. For somewhat better synchronization, a user
can keep the U_MSR_PMON_CTL.ev_sel at 0x0 while enabled and write it with a valid
value just prior to unfreezing the registers in other boxes.
2.1.2 Reading the Sample Interval
Software can poll the counters whenever it chooses.
a) Polling - before reading, it is recommended that software freeze the counters in each box in which
counting is to take place (by setting *_PMON_BOX_CTL.frz_en and .frz to 1). After reading the event
counts from the counter registers, the monitoring agent can choose to reset the event counts to avoid
event-count wrap-around; or resume the counter register without resetting their values. The latter
choice will require the monitoring agent to check and adjust for potential wrap-around situations.