Intel Xeon E5-2600 Series - Ubox PMON State - Counter;Control Pairs; U_MSR_PMON_CTL{1-0} Register - Field Definitions; U_MSR_PMON_CTR{1-0} Register - Field Definitions

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring
20 Reference Number: 327043-001
2.2.3.2 UBox PMON state - Counter/Control Pairs
The following table defines the layout of the UBox performance monitor control registers. The main
task of these configuration registers is to select the event to be monitored by their respective data
counter (.ev_sel, .umask). Additional control bits are provided to shape the incoming events (e.g.
.invert, .edge_det, .thresh) as well as provide additional functionality for monitoring software (.rst).
The UBox performance monitor data registers are 44-bit wide. Should a counter overflow (a carry out
from bit 43), the counter will wrap and continue to collect events.
If accessible, software can continuously read the data registers without disabling event collection.
The Global UBox PMON registers also include a fixed counter that increments at UCLK for each cycle it
is enabled.
Table 2-2. U_MSR_PMON_CTL{1-0} Register – Field Definitions
Field Bits Attr
HW
Reset
Val
Description
rsv 31:29 RV 0 Reserved (?)
thresh 28:24 RW 0 Threshold used in counter comparison.
invert 23 RW 0 Invert comparison against Threshold.
0 - comparison will be ‘is event increment >= threshold?’.
1 - comparison is inverted - ‘is event increment < threshold?’
NOTE: .invert is in series following .thresh, Due to this, the
.thresh field must be set to a non-0 value. For events that
increment by no more than 1 per cycle, set .thresh to 0x1.
Also, if .edge_det is set to 1, the counter will increment when a 1
to 0 transition (i.e. falling edge) is detected.
en 22 RW 0 Local Counter Enable.
rsv 21:20 RV 0 Reserved. SW must write to 0 for proper operation.
rsv 19 RV 0 Reserved (?)
edge_det 18 RW 0 When set to 1, rather than measuring the event in each cycle it
is active, the corresponding counter will increment when a 0 to 1
transition (i.e. rising edge) is detected.
When 0, the counter will increment in each cycle that the event
is asserted.
NOTE: .edge_det is in series following .thresh, Due to this, the
.thresh field must be set to a non-0 value. For events that
increment by no more than 1 per cycle, set .thresh to 0x1.
rst 17 WO 0 When set to 1, the corresponding counter will be cleared to 0.
umask 15:8 RW 0 Select subevents to be counted within the selected event.
ev_sel 7:0 RW 0 Select event to be counted.
Table 2-3. U_MSR_PMON_CTR{1-0} Register – Field Definitions
Field Bits Attr
HW
Reset
Val
Description
rsv 63:44 RV 0 Reserved (?)
event_count 43:0 RW-V 0 44-bit performance event counter