Intel Xeon E5-2600 Series - Cbo Filter Register (Cn_Msr_Pmon_Box_Filter); Cn_Msr_Pmon_Ctr{3-0} Register - Field Definitions

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring
28 Reference Number: 327043-001
The CBo performance monitor data registers are 44b wide. Should a counter overflow (a carry out
from bit 43), the counter will wrap and continue to collect events.If accessible, software can
continuously read the data registers without disabling event collection.
2.3.3.3 CBo Filter Register (Cn_MSR_PMON_BOX_FILTER)
In addition to generic event counting, each CBo provides a MATCH register that allows a user to filter
various traffic as it applies to specific events (see Event Section for more information). LLC_LOOKUP
may be filtered by the cacheline state, QPI_CREDITS may be filtered by link while TOR_INSERTS and
TOR_OCCUPANCY may be filtered by the opcode of the queued request as well as the corresponding
NodeID.
Any of the CBo events may be filtered by Thread/Core-ID. To do so, the control register’s .tid_en bit
must be set to 1 and the tid field in the FILTER register filled out.
invert 23 RW-V 0 Invert comparison against Threshold.
0 - comparison will be ‘is event increment >= threshold?’.
1 - comparison is inverted - ‘is event increment < threshold?’
NOTE: .invert is in series following .thresh, Due to this, the
.thresh field must be set to a non-0 value. For events that
increment by no more than 1 per cycle, set .thresh to 0x1.
Also, if .edge_det is set to 1, the counter will increment when a 1
to 0 transition (i.e. falling edge) is detected.
en 22 RW-V 0 Local Counter Enable.
rsv 21:20 RV 0 Reserved; SW must write to 0 else behavior is undefined.
tid_en 19 RW-V 0 TID Filter Enable
edge_det 18 RW-V 0 When set to 1, rather than measuring the event in each cycle it
is active, the corresponding counter will increment when a 0 to 1
transition (i.e. rising edge) is detected.
When 0, the counter will increment in each cycle that the event
is asserted.
NOTE: .edge_det is in series following .thresh, Due to this, the
.thresh field must be set to a non-0 value. For events that
increment by no more than 1 per cycle, set .thresh to 0x1.
rst 17 WO 0 When set to 1, the corresponding counter will be cleared to 0.
rsv 16 RV 0 Reserved. SW must write to 0 else behavior is undefined.
umask 15:8 RW-V 0 Select subevents to be counted within the selected event.
ev_sel 7:0 RW-V 0 Select event to be counted.
Table 2-11. Cn_MSR_PMON_CTR{3-0} Register – Field Definitions
Field Bits Attr
HW
Reset
Val
Description
rsv 63:44 RV 0 Reserved (?)
event_count 43:0 RW-V 0 44-bit performance event counter
Table 2-10. Cn_MSR_PMON_CTL{3-0} Register – Field Definitions (Sheet 2 of 2)
Field Bits Attr
HW
Reset
Val
Description