Intel Xeon E5-2600 Series - Intel QPI PMON State - Counter;Control Pairs; Q_Py_Pci_Pmon_Box_Ctl Register - Field Definitions; Q_Py_Pci_Pmon_Ctl{3-0} Register - Field Definitions

Reference Number: 327043-001 89
Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring
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2.7.3.2 Intel® QPI PMON state - Counter/Control Pairs
The following table defines the layout of the Intel® QPI performance monitor control registers. The
main task of these configuration registers is to select the event to be monitored by their respective
data counter (.ev_sel, .umask, .ev_sel_ext). Additional control bits are provided to shape the
incoming events (e.g. .invert, .edge_det, .thresh) as well as provide additional functionality for
monitoring software (.rst).
Table 2-85. Q_Py_PCI_PMON_BOX_CTL Register – Field Definitions
Field Bits Attr
HW
Reset
Val
Description
rsv 31:18 RV 0 Reserved (?)
rsv 17 RV 0 Reserved; SW must write to 0 else behavior is undefined.
frz_en 16 WO 0 Freeze Enable.
If set to 1 and a freeze signal is received, the counters will be
stopped or ‘frozen’, else the freeze signal will be ignored.
rsv 15:9 RV 0 Reserved (?)
frz 8 WO 0 Freeze.
If set to 1 and the .frz_en is 1, the counters in this box will be
frozen.
rsv 7:2 RV 0 Reserved (?)
rst_ctrs 1 WO 0 Reset Counters.
When set to 1, the Counter Registers will be reset to 0.
rst_ctrl 0 WO 0 Reset Control.
When set to 1, the Counter Control Registers will be reset to 0.
Table 2-86. Q_Py_PCI_PMON_CTL{3-0} Register – Field Definitions (Sheet 1 of 2)
Field Bits Attr
HW
Reset
Val
Description
thresh 31:24 RW-V 0 Threshold used in counter comparison.
invert 23 RW-V 0 Invert comparison against Threshold.
0 - comparison will be ‘is event increment >= threshold?’.
1 - comparison is inverted - ‘is event increment < threshold?’
NOTE: .invert is in series following .thresh, Due to this, the
.thresh field must be set to a non-0 value. For events that
increment by no more than 1 per cycle, set .thresh to 0x1.
Also, if .edge_det is set to 1, the counter will increment when a 1
to 0 transition (i.e. falling edge) is detected.
en 22 RW-V 0 Local Counter Enable.
ev_sel_ext 21 RW-V 0 Extentsion bit to the Event Select field.
rsv 20 RV 0 Reserved. SW must write to 0 for proper operation.
rsv 19 RV 0 Reserved (?)