Intel Xeon E5-2600 Series - PCU_MSR_PMON_CTR{3-0} Register - Field Definitions

Reference Number: 327043-001 75
Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring
The PCU performance monitor data registers are 48-bit wide. Should a counter overflow (a carry out
from bit 47), the counter will wrap and continue to collect events.
If accessible, software can continuously read the data registers without disabling event collection.
Context sensitive filtering is provided for through the PCU_MSR_PMON_BOX_FILTER register.
invert 23 RW-V 0 Invert comparison against Threshold.
0 - comparison will be ‘is event increment >= threshold?’.
1 - comparison is inverted - ‘is event increment < threshold?’
NOTE: .invert is in series following .thresh, Due to this, the
.thresh field must be set to a non-0 value. For events that
increment by no more than 1 per cycle, set .thresh to 0x1.
Also, if .edge_det is set to 1, the counter will increment when a 1
to 0 transition (i.e. falling edge) is detected.
en 22 RW-V 0 Local Counter Enable.
rsv 21:20 RV 0 Reserved. SW must write to 0 for proper operation.
rsv 19 RV 0 Reserved (?)
edge_det 18 RW-V 0 When set to 1, rather than measuring the event in each cycle it
is active, the corresponding counter will increment when a 0 to 1
transition (i.e. rising edge) is detected.
When 0, the counter will increment in each cycle that the event
is asserted.
NOTE: .edge_det is in series following .thresh, Due to this, the
.thresh field must be set to a non-0 value. For events that
increment by no more than 1 per cycle, set .thresh to 0x1.
rst 17 WO 0 When set to 1, the corresponding counter will be cleared to 0.
rsv 16 RV 0 Reserved (?)
occ_sel 15:14 RW-V 0 Select which of three occupancy counters to use.
01 - Cores in C0
10 - Cores in C3
11 - Cores in C6
rsv 13:8 RV 0 Reserved (?)
ev_sel 7:0 RW-V 0 Select event to be counted.
NOTE: Bit 7 denotes whether the event requires the use of an
occupancy subcounter.
Table 2-76. PCU_MSR_PMON_CTR{3-0} Register – Field Definitions
Field Bits Attr
HW
Reset
Val
Description
rsv 63:48 RV 0 Reserved (?)
event_count 47:0 RW-V 0 48-bit performance event counter
Table 2-75. PCU_MSR_PMON_CTL{3-0} Register – Field Definitions (Sheet 2 of 2)
Field Bits Attr
HW
Reset
Val
Description