Intel Xeon E5-2600 Series - Q_Py_Pci_Pmon_Pkt_Mask1 Registers; Q_Py_Pci_Pmon_Pkt_Mask0 Registers

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring
92 Reference Number: 327043-001
2.7.3.3.1 Events Derived from Packet Filters
Following is a selection of common events that may be derived by using the Intel® QPI packet
matching facility. The Match/Mask columns correspond to the Match0/Mask0 registers. For the cases
where additional fields need to be specified, they will be noted.
Table 2-90. Q_Py_PCI_PMON_PKT_MASK1 Registers
Field Bits
HW
Reset
Val
Description
--- 31:20 0x0 Reserved; Must write to 0 else behavior is undefined.
RDS 19:16 0x0 Response Data State (valid when MC == DRS and Opcode == 0x0-
2). Bit settings are mutually exclusive.
b1000 - Modified
b0100 - Exclusive
b0010 - Shared
b0001 - Forwarding
b0000 - Invalid (Non-Coherent)
--- 15:4 0x0 Reserved; Must write to 0 else behavior is undefined.
RNID_3_0 3:0 0x0 Remote Node ID(3:0 - Leat Significant Bits)
Table 2-91. Q_Py_PCI_PMON_PKT_MASK0 Registers
Field Bits
HW
Reset
Val
Description
RNID_4 31 0x0 Remote Node ID(Bit 4 - Most Significant Bit)
--- 30:18 0x0 Reserved; Must write to 0 else behavior is undefined.
DNID 17:13 0x0 Destination Node ID
MC 12:9 0x0 Message Class
OPC 8:5 0x0 Opcode
See Section 2.10, “Packet Matching Reference” for a listing of
opcodes that may be filtered per message class.
VNW 4:3 0x0 Virtual Network
--- 2:0 0x0 Reserved; Must write to 0 else behavior is undefined.