Design Guide 51
Platform Clock Routing Guidelines
4.3 Clock Driver Power Delivery
Designers must take special care to provide a quiet VDDA supply to the Ref VDD, VDDA and the
48 MHz VDD. These VDDA signals are especially sensitive to switching noise induced by the
other VDDs on the clock chip. They are also sensitive to switching noise generated elsewhere in
the system such as the processor voltage regulator. It is recommended that a ground flood be placed
directly under the clock chip to provide a low impedance connection for the VSS pins. In addition,
power vias should be distributed evenly throughout the ground flood.
Note: For all power connections to planes, decoupling capacitors, and vias, the maximum trace width
allowable and shortest possible lengths should be used to ensure lowest possible inductance.
4.4 EMI Constraints
Clocks are a significant contributor to EMI. The following recommendations can aid in EMI
reduction:
• Maintain uniform spacing between the two halves of differential clocks.
• Route clocks on physical layer adjacent to the VSS reference plane only.
• Turn off all unused clocks.
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