Intel Xeon User Manual

Design Guide 213
Layout Checklist
14.2 Intel
®
E7500 MCH Layout Checklist
Table 14-2. MCH Layout Checklist (Sheet 1 of 3)
Checklist Items Recommendations Comments
Host Interface
ADS#
AP[1:0]
BINIT#
BNR#
BPRI#
BREQ0#
1
CPURST#
2
DBSY#
DEFER#
HA[35:3]#
3
HD[63:0]#
4
HADSTB[1:0]#
5
HDSTBN[3:0]#
6
HDSTBP[3:0]#
7
HIT#
HITM#
HLOCK#
HREQ[4:0]#
8
HTRDY#
9
DP[3:0]#
DRDY#
RS[2:0]#
RSP#
XERR#
10
DBI[3:0]#
• See processor section of this checklist.
DDR Interfaces A & B / Connector
General
Guidelines
• Route interface 50 Ω nominal impedance,
± 10%.
• 5 on 15 is maintained for Data/Strobe/
CMD signals; 5 on 7 is maintained for CK/
CK# signals.
• If using the recommended stackup, outer
layer routing of DDR signals should be
kept to a minimum (except for reference
voltages). Via up close to passive
devices, and immediately via back down
following the device.
• Try to maintain same ground reference
when transitioning layers—add stitching
via if reference plane changes.
• Connect termination resistors directly to
termination plane (flood is on outer layer).
• Space traces out as much as possible
through the DIMMs.
• All traces are routed 1.8" to 6.0" from
MCH to first DIMM connector, and 0.8" to
1.2” between connectors.

Intel Xeon Specifications

General

Brand	Intel
Model	Xeon
Category	Processor
Language	English