Intel Xeon User Manual

Layout Checklist
214 Design Guide
DQ[63:0]
CB[7:0]
DQS[17:0]
• Route entirely on the same layer from
MCH to DIMM to termination (no layer
transitions). Place the 10
Ω series resistor
< 800 mils from the first DIMM connector.
All signals in a data group must be length
matched to the associated DQS within
± 100 mils. In addition, each DQS must
be length matched to its associated
command clock within ± 1.75". Place
termination resistor within 800 mils from
the last DIMM connector.
• Refer to Section 6.2.
RAS#
CAS#
WE#
MA[12:0]
BA[1:0]
• Length match to command clock within
2 in. Place termination resistor within 800
mills from last DIMM connector. No more
then 2 vias/layer transitions, not including
breakout and passive devices.
• Refer to Section 6.4.
CS[7:0]# • Place termination resistor within 3" from
the connector.
• Refer to Section 6.5.
CMDCLK[3:0]
CMDCLK[3:0]#
• Clock signals within a differential pair
must be matched to each other within ±
2 mils. These signals must be routed 5 on
15, and must be at least 20 mils away
from any other signal. Total length must
be between 2.1” and 10.0”.
• Refer to Section 6.3.
CKE • Route 40
Ω using a 7.5 mil wide trace.
The CKE signal must be length matched
to the clock signal at each DIMM within
2". Place termination resistor within
800 mils from last DIMM connector.
• Refer to Section 6.5.
RCVENIN#
RCVENOUT#
• RCVEN signal must be 15” ± 100 mils
long, pulled up to VTT using 47
Ω ± 2%.
• Refer to Section 6.7.
DDRCOMP • Place pull-up
resistor within 1" of the
MCH.
• Refer to Section 6.8.
DDRCVOL
DDRCVOH
• Place resistive network within 1" of the
MCH.
• Refer to Section 6.8.
Decoupling • Spread termination decoupling capacitors
evenly around the termination plane.
• Spread 2.5 V decoupling capacitors
evenly around the DIMMs.
• Refer to Section 6.11.
Hub Interfaces
General
Guidelines
• Hublink data spacing of 5 on 15 is
maintained for data, and 5 on 35 is
maintained for strobes.
• Traces are spaced out as much as
possible through the BGA.
• Hublink data group signals are routed on
the same layer, transitioning together if a
layer change is required.
• Maximum length of 20" (stripline routing).
• Length match HI 2.0 strobes within 1"
from data. Length match according to
Figure 7-2.
• HI 1.5: Length match strobes and data
± 100 mils.
• Refer to Section 7.2.1 and
Section 7.3.1of this document.
Table 14-2. MCH Layout Checklist (Sheet 2 of 3)
Checklist Items Recommendations Comments

Intel Xeon Specifications

General

Brand	Intel
Model	Xeon
Category	Processor
Language	English