Intel Xeon Datasheet

Intel® Xeon™ Processor with 800 MHz System Bus
Datasheet 15
2.3.2 Phase Lock Loop (PLL) and Filter
V
CCA
and V
CCIOPLL
are power sources required by the PLL clock generators on the Intel® Xeon™
processor with 800 MHz system bus. Since these PLLs are analog in nature, they require quiet
power supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O
timings as well as internal core timings (i.e., maximum frequency). To prevent this degradation,
these supplies must be low pass filtered from V
TT
.
The AC low-pass requirements are as follows:
• < 0.2 dB gain in pass band
• < 0.5 dB attenuation in pass band < 1 Hz
• > 34 dB attenuation from 1 MHz to 66 MHz
• > 28 dB attenuation from 66 MHz to core frequency
The filter requirements are illustrated in Figure 1.
NOTES:
1. Diagram not to scale.
2. No specifications for frequencies beyond f
core
(core frequency).
3. f
peak
, if existent, should be less than 0.05 MHz.
4. f
core
represents the maximum core frequency supported by the platform.
2.4 Voltage Identification (VID)
The Voltage Identification (VID) specification for the Intel® Xeon™ processor with 800 MHz
system bus is defined by the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-
Down (EVRD) 10.0 Design Guidelines and Voltage Regulator Module (VRM) and Enterprise
Voltage Regulator-Down (EVRD) 10.1 Design Guidelines. The voltage set by the VID signals is the
maximum voltage allowed by the processor (please see Section 2.11.2 for V
CC
overshoot
specifications). VID signals are open drain outputs, which must be pulled up to V
TT
. Please refer to
Figure 1. Phase Lock Loop (PLL) Filter Requirements
CS00141
0.2 dB
0 dB
x dB
–28 dB
–34 dB
66 MHz 1.67 GHz1 MHz1 HzDC fpeak fcore
Passband
High
Frequency
<50 kHz 500 MHz

Intel Xeon Specifications

General

Brand	Intel
Model	Xeon
Category	Processor
Language	English