Intel Xeon Datasheet

Intel® Xeon™ Processor with 800 MHz System Bus
40 Datasheet
BINIT# I/O BINIT# (Bus Initialization) may be observed and driven by all processor front side bus
agents and if used, must connect the appropriate pins of all such agents. If the BINIT#
driver is enabled during power on configuration, BINIT# is asserted to signal any bus
condition that prevents reliable future information.
If BINIT# observation is enabled during power-on configuration (see Figure 7.1) and
BINIT# is sampled asserted, symmetric agents reset their bus LOCK# activity and bus
request arbitration state machines. The bus agents do not reset their I/O Queue (IOQ)
and transaction tracking state machines upon observation of BINIT# assertion. Once the
BINIT# assertion has been observed, the bus agents will re-arbitrate for the front side
bus and attempt completion of their bus queue and IOQ entries.
If BINIT# observation is disabled during power-on configuration, a central agent may
handle an assertion of BINIT# as appropriate to the error handling architecture of the
system.
Since multiple agents may drive this signal at the same time, BINIT# is a wired-OR signal
which must connect the appropriate pins of all processor front side bus agents. In order
to avoid wired-OR glitches associated with simultaneous edge transitions driven by
multiple drivers, BINIT# is activated on specific clock edges and sampled on specific
clock edges
4
BNR# I/O BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is unable
to accept new bus transactions. During a bus stall, the current bus owner cannot issue
any new transactions.
Since multiple agents might need to request a bus stall at the same time, BNR# is a
wired-OR signal which must connect the appropriate pins of all processor front side bus
agents. In order to avoid wired-OR glitches associated with simultaneous edge
transitions driven by multiple drivers, BNR# is activated on specific clock edges and
sampled on specific clock edges.
4
BOOT_
SELECT
I The BOOT_SELECT input informs the processor whether the platform supports the
Intel® Xeon™ processor with 800 MHz system bus. The processor will not operate if this
signal is low. This input has a weak pull-up to V
TT
.
BPM[5:0]# I/O BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They
are outputs from the processor which indicate the status of breakpoints and
programmable counters used for monitoring processor performance. BPM[5:0]# should
connect the appropriate pins of all front side bus agents.
BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is a
processor output used by debug tools to determine processor debug readiness.
BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is used
by debug tools to request debug operation of the processors.
BPM[5:4]# must be bussed to all bus agents.
These signals do not have on-die termination and must be terminated at the end agent.
3
BPRI# I BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor front
side bus. It must connect the appropriate pins of all processor front side bus agents.
Observing BPRI# active (as asserted by the priority agent) causes all other agents to
stop issuing new requests, unless such requests are part of an ongoing locked operation.
The priority agent keeps BPRI# asserted until all of its requests are completed, then
releases the bus by deasserting BPRI#.
4
Table 20. Signal Definitions (Sheet 2 of 9)
Name Type Description Notes

Intel Xeon Specifications

General

Brand	Intel
Model	Xeon
Category	Processor
Language	English