Intel® Xeon™ Processor with 800 MHz System Bus
Datasheet 43
FERR#/PBE# O FERR#/PBE# (floating-point error/pending break event) is a multiplexed signal and its
meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/PBE#
indicates a floating-point error and will be asserted when the processor detects an
unmasked floating-point error. When STPCLK# is not asserted, FERR#/PBE# is similar
to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with
systems using MS-DOS*-type floating-point error reporting. When STPCLK# is asserted,
an assertion of FERR#/PBE# indicates that the processor has a pending break event
waiting for service. The assertion of FERR#/PBE# indicates that the processor should be
returned to the Normal state. For additional information on the pending break event
functionality, including the identification of support of the feature and enable/disable
information, refer to Vol. 3 of the IA-32 Software Developer’s Manual and the Intel
Processor Identification and the CPUID Instruction application note.
This signal does not have on-die termination and must be terminated at the end
agent.
3
FORCEPR# I The FORCEPR# input can be used by the platform to force the Intel® Xeon™ processor
with 800 MHz system bus to activate the Thermal Control Circuit (TCC). The TCC will
remain active until the system deasserts FORCEPR#.
GTLREF I GTLREF determines the signal reference level for GTL+ input pins. GTLREF is used by
the GTL+ receivers to determine if a signal is a logical 0 or a logical 1.
HIT#
HITM#
I/O
I/O
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results.
Any front side bus agent may assert both HIT# and HITM# together to indicate that it
requires a snoop stall, which can be continued by reasserting HIT# and HITM# together.
Since multiple agents may deliver snoop results at the same time, HIT# and HITM# are
wired-OR signals which must connect the appropriate pins of all processor front side bus
agents. In order to avoid wired-OR glitches associated with simultaneous edge
transitions driven by multiple drivers, HIT# and HITM# are activated on specific clock
edges and sampled on specific clock edges.
4
IERR# O IERR# (Internal Error) is asserted by a processor as the result of an internal error.
Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the
processor front side bus. This transaction may optionally be converted to an external
error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted
until the assertion of RESET#.
This signal does not have on-die termination and must be terminated at the end agent.
3
IGNNE# I IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric
error and continue to execute noncontrol floating-point instructions. If IGNNE# is
deasserted, the processor generates an exception on a noncontrol floating-point
instruction if a previous floating-point instruction caused an error. IGNNE# has no effect
when the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of the
corresponding I/O write bus transaction.
3
INIT# I INIT# (Initialization), when asserted, resets integer registers inside all processors without
affecting their internal caches or floating-point registers. Each processor then begins
execution at the power-on Reset vector configured during power-on configuration. The
processor continues to handle snoop requests during INIT# assertion. INIT# is an
asynchronous signal and must connect the appropriate pins of all processor front side
bus agents.
If INIT# is sampled active on the active to inactive transition of RESET#, then the
processor executes its Built-in Self-Test (BIST).
3
Table 20. Signal Definitions (Sheet 5 of 9)
Name Type Description Notes
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