Intel Xeon Datasheet

Intel® Xeon™ Processor with 800 MHz System Bus
Datasheet 45
REQ[4:0]# I/O REQ[4:0]# (Request Command) must connect the appropriate pins of all processor front
side bus agents. They are asserted by the current bus owner to define the currently
active transaction type. These signals are source synchronous to ADSTB[1:0]#. Refer to
the AP[1:0]# signal description for details on parity checking of these signals.
4
RESET# I Asserting the RESET# signal resets all processors to known states and invalidates their
internal caches without writing back any of their contents. For a power-on Reset,
RESET# must stay active for at least 1 ms after V
CC and BCLK have reached their proper
specifications. On observing active RESET#, all front side bus agents will deassert their
outputs within two clocks. RESET# must not be kept asserted for more than 10 ms while
PWRGOOD is asserted.
A number of bus signals are sampled at the active-to-inactive transition of RESET# for
power-on configuration. These configuration options are described in the Section 7.1.
This signal does not have on-die termination and must be terminated at the end agent.
4
RS[2:0]# I RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for
completion of the current transaction), and must connect the appropriate pins of all
processor front side bus agents.
4
RSP# I RSP# (Response Parity) is driven by the response agent (the agent responsible for
completion of the current transaction) during assertion of RS[2:0]#, the signals for which
RSP# provides parity protection. It must connect to the appropriate pins of all processor
front side bus agents.
A correct parity signal is high if an even number of covered signals are low and low if an
odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also high, since
this indicates it is not being driven by any agent guaranteeing correct parity.
4
SKTOCC# O SKTOCC# (Socket occupied) will be pulled to ground by the processor to indicate that
the processor is present. There is no connection to the processor silicon for this signal.
SLEW_CTRL I The front side bus slew rate control input, SLEW_CTRL, is used to establish distinct edge
rates for middle and end agents.
SLP# I SLP# (Sleep), when asserted in Stop-Grant state, causes processors to enter the Sleep
state. During Sleep state, the processor stops providing internal clock signals to all units,
leaving only the Phase-Lock Loop (PLL) still operating. Processors in this state will not
recognize snoops or interrupts. The processor will only recognize the assertion of the
RESET# signal, deassertion of SLP#, and removal of the BCLK input while in Sleep
state. If SLP# is deasserted, the processor exits Sleep state and returns to Stop-Grant
state, restarting its internal clock signals to the bus and processor core units.
3
SMB_PRT O The SMBus present (SMB_PRT) pin is defined to inform the platform if the installed
processor includes SMBus components such as the integrated thermal sensor and the
processor information ROM (PIROM). This pin is tied to VSS by the processor if these
features are not present. Platforms using this pin should use a pull up resistor to the
appropriate voltage level for the logic tied to this pin. Because this pin does not connect
to the processor silicon, any platform voltage and termination value is acceptable.
SMI# I SMI# (System Management Interrupt) is asserted asynchronously by system logic. On
accepting a System Management Interrupt, processors save the current state and enter
System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the
processor begins program execution from the SMM handler.
If SMI# is asserted during the deassertion of RESET# the processor will tri-state its
outputs.
3
STPCLK# I STPCLK# (Stop Clock), when asserted, causes processors to enter a low power Stop-
Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops
providing internal clock signals to all processor core units except the front side bus and
APIC units. The processor continues to snoop bus transactions and service interrupts
while in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its
internal clock to all units and resumes execution. The assertion of STPCLK# has no
effect on the bus clock; STPCLK# is an asynchronous input.
3
Table 20. Signal Definitions (Sheet 7 of 9)
Name Type Description Notes

Intel Xeon Specifications

General

Brand	Intel
Model	Xeon
Category	Processor
Language	English