Intel Xeon Datasheet

Intel® Xeon™ Processor with 800 MHz System Bus
Datasheet 47
VIDPWRGD I The processor requires this input to determine that the supply voltage for BSEL[1:0] and
VID[5:0] is stable and within specification.
V
SSA
IV
SSA
provides an isolated, internal ground for internal PLL’s. Do not connect directly to
ground. This pin is to be connected to V
CCA
and V
CCIOPLL
through a discrete filter circuit.
V
TT
P The front side bus termination voltage input pins. Refer to Table 9 for further details.
VTTEN O The VTTEN can be used as an output enable for the VTT regulator in the event an
incompatible processor is inserted into the platform. There is no connection to the
processor silicon for this signal and it must be pulled up through a resistor.
NOTES:
1. The Intel® Xeon™ processor with 800 MHz system bus only supports BR0# and BR1#. However, platforms must terminate
BR2# and BR3# to V
TT
.
2. For this pin on Intel® Xeon™ processor with 800 MHz system bus, the maximum number of symmetric agents is one.
Maximum number of central agents is zero.
3. For this pin on Intel® Xeon™ processor with 800 MHz system bus, the maximum number of symmetric agents is two.
Maximum number of central agents is zero.
4. For this pin on Intel® Xeon™ processor with 800 MHz system bus, the maximum number of symmetric agents is two.
Maximum number of central agents is one.
Table 20. Signal Definitions (Sheet 9 of 9)
Name Type Description Notes

Intel Xeon Specifications

General

Brand	Intel
Model	Xeon
Category	Processor
Language	English