Keithley 2000 Repair Manual

TEST BANK: DC/OHM
Test 300.1 — FRONT END LO
Bank DC/OHM
Inputs Open
Expected Value 0 volts
Limits 0.01 volts
Fault Message FRONT END LO
Description This test is for the DC volts front end LO path. Control line DIVLO is high
making the U120 comparator output (pin 2) open collector. Q114 is on due
to the gate being pulled low by R164. Signal LO is connected to SIG/100
through Q114 and divider R117.
The DIVTAP control line at U115 (pin 11) is pulled high to turn on Q108.
This routes SIG/100 LO through Q108 to the unity gain buffer U113. The
signal at the output of U113 is now called BUFCOM and goes through R314
to S4 of U163. It then goes to the A/D MUX which is configured for
× 1 gain.
Measure 0V at AD_IN.
Bit patterns
Bit pattern Register
QQ
87654321
—U106—
110v1111
QQ
87654321
—U109—
00101111
QQ
87654321
—U134—
1v10000v
—U130—
10111101
QQ
87654321
—U121—
01110001
ACDC_STB
MUX_STB
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
2-32 Troubleshooting

Keithley 2000 Specifications

General

Digits	6.5
DC Voltage Range	100 mV to 1000 V
AC Voltage Range	100 mV to 750 V
Resistance Range	100 Ω to 100 MΩ
Connectivity	IEEE-488 (GPIB)
Display Type	VFD