Lattice Semiconductor MIPI - IP Parameter Configuration; Core IP Settings and Options

MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge Soft IP
User Guide
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FPGA-IPUG-02003-1.2 15
3. Parameter Settings
Table 3.1 shows the parameters used to generate MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP.
Table 3.1. MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP Parameter Settings
Parameter
Attribute
Options
Description
Number of Rx channels
User-input
1 or 2
Number of MIPI D-PHY channels.
If 2 is selected, the following Rx settings will be applied
to both Rx channels
Rx Interface
Fixed
MIPI DSI
Receive interface
Number of Rx lanes
Fixed
4
Number of MIPI D-PHY data lanes
Rx gearing
Read-only
8 or 16
Gearbox ratio of receive interface, automatically
selected based on Rx data rate (see Reset and Clocking
section on page 13)
Rx D-PHY IP
Fixed
Hard D-PHY
MIPI D-PHY Implementation
Number of Tx channels
User-input
1 or 2
Number of LVDS channels
Tx Interface
Fixed
LVDS
Transmit interface (FPD-Link)
Number of Tx lanes
Read-only
3 or 4
Derived from data type: 3 lanes for RGB666 while 4
lanes for RGB888
Tx gearing
Read-only
7 or 14
Gearbox ratio of transmit interface, automatically
selected based on Rx data rate (see Reset and Clocking
section on page 13)
Rx Line Rate
User-input
See Table 2.4
Data rate per MIPI D-PHY lane
Tx Line Rate
Read-only
See Table 2.3
Data rate per LVDS lane
D-PHY Clock Frequency
Read-only
See Table 2.3
MIPI D-PHY clock frequency (DCK).
t
HS-SETTLE
MIPI D-PHY timing parameter is also derived
from this setting (85 ns + 6 UI).
t
HS-SETTLE
counter is implemented in byte clock domain.
The expected actual t
HS-SETTLE
is ~2 byte clock cycles
more than the computed value.
D-PHY Clock Mode
User-input
Continuous or Non-
continuous
MIPI D-PHY clock mode
Byte Clock Frequency
Read-only
See Table 2.3
Byte clock frequency
Pixel Clock Frequency
Read-only
See Table 2.3
Pixel clock frequency
Eclk Frequency
Read-only
See Table 2.3
Serializer clock frequency
LVDS Clock Frequency
Read-only
See Table 2.3
LVDS clock frequency
Reference Clock Frequency
Read-only
See Table 2.3
Reference clock frequency
Miscellaneous Signals
User-input
Marked or Unmarked
Brings out miscellaneous status signals to port
Data Type
User-input
RGB888 or RGB666
Supported MIPI DSI data types
RGB666 Type
User-input
Packed or Loosely
Packed
Selects between RGB666 Packed and Loosely Packed
formats