MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge Soft IP
User Guide
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22 FPGA-IPUG-02003-1.2
Table 4.2. Testbench Directives (Continued)
Number of bytes of active pixels per line
Number of bytes of Horizontal Sync Active Payload (used for Non-burst sync pulse)
Number of bytes of BLLP Payload (used for HS data blanking)
Number of bytes of Horizontal Back Porch Payload (used for HS data blanking, and in LP
blanking for Non-burst sync pulse mode)
Number of bytes of Horizontal Front Porch Payload (used for HS data blanking, and in LP
blanking for Non-burst sync pulse mode)
Number of Vertical Sync Active Lines
Number of Vertical Back Porch Lines
Number of Vertical Front Porch Lines
Used to enable/disable transmission of EOTP packet
0 – EOTP packet is disabled
1 – EOTP packet is enabled
Used to set the duration (in ps) for BLLP low-power state (used for LP blanking)
Used to set the duration (in ps) for Horizontal Back Porch low-power state (used for LP
blanking in Non-burst sync events and Burst mode)
Used to set the duration (in ps) for Horizontal Front Porch low-power state (used for LP
blanking in Non-burst sync events and Burst mode)
Used to set the video mode type to Non-burst sync events (Not supported by DUT)
Used to set the video mode type to Burst Mode (Not supported by DUT)
Used to set the video mode type to Non-burst sync pulse
The testbench has default settings for D-PHY timing parameters. Refer to Table 14 of MIPI D-PHY Specification
version 1.1 for information regarding D-PHY timing requirements. To modify the D-PHY timing parameters, user can set
the following testbench directives:
Table 4.3. Testbench Directives for D-PHY Timing Parameters
Used to set T-LPX (in ps)
Used to set T-CLK-PREPARE (in ps)
Used to set T-CLK-ZERO (in ps)
Used to set T-CLK-PRE (in ps)
Used to set T-CLK-POST (in ps)
Used to set T-CLK-TRAIL (in ps)
Used to set T-HS-PREPARE (in ps)
Used to set T-HS-ZERO (in ps)
Used to set T-HS-TRAIL (in ps)
By default, the testbench automatically calculates the reference clock period for HS_LP clock mode. The user can
override the clock period by defining the following testbench directive:
Table 4.4. Testbench Directives for Reference Clock Period
Used to set the Reference clock period input to the design (in ps)
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