MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge Soft IP
User Guide
© 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
28 FPGA-IPUG-02003-1.2
Appendix A. Resource Utilization
Table A.1 lists resource utilization for Lattice CrossLink FPGAs using the MIPI DSI to OpenLDI/FPD-Link/LVDS Interface
Bridge IP. The performance and utilization data target an LIF-MD6000-6MG81I device with –6 speed grade using Lattice
Diamond 3.8 and Lattice Synthesis Engine. Performance may vary when using a different software version or targeting
a different device density or speed grade within the CrossLink family. Programmable I/Os do not count miscellaneous
status signals. The values of f
MAX
shown are based on continuous byte clock. The Target f
MAX
column shows target byte
clock frequency for each configuration. See the Reset and Clocking section on page 13 for more details on supported
clock frequencies.
Table A.1. Resource Utilization
IP User-Configurable
Parameters
Single Rx to Single Tx,
RX_GEAR=8, TX_GEAR=7,
RGB888,
Non-continuous D-PHY clock
Single Rx to Single Tx,
RX_GEAR=16, TX_GEAR=14,
RGB888,
Non-continuous D-PHY clock
Single Rx to Dual Tx,
RX_GEAR=8, TX_GEAR=7,
RGB888,
Non-continuous D-PHY clock
Single Rx to Dual Tx,
RX_GEAR=16, TX_GEAR=14,
RGB888,
Non-continuous D-PHY clock
Dual Rx to Dual Tx,
RX_GEAR=8, TX_GEAR=7,
RGB888,
Non-continuous D-PHY clock
Dual Rx to Dual Tx,
RX_GEAR=16, TX_GEAR=14,
RGB888,
Non-continuous D-PHY clock
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