Lattice Semiconductor MIPI User Manual

MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge Soft IP
User Guide
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Appendix B. What is Not Supported
The MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP does not support the following features:
 1:2 (duplicate display) and 2:1 MIPI DSI to FPD-Link configurations
 PPI (PHY Protocol Interface)
 Low-level protocol error detection (SoT Error, SoT Sync Error, and so on.)
 ECC check and error detection/correction of packet header in a short and a long packet
 Checksum calculation and error detection in long packet
 Command mode operation in MIPI DSI
 Non-burst mode with sync events and burst mode in MIPI DSI
 DCS parsing in MIPI DSI
 Interlaced video scan mode
The MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP has the following design limitations:
 Maximum value of word count in a long packet is 16'hFFF5
 Minimum value of word count in a long packet when RX_GEAR=16 is 16'h0002 when byte clock speed is 65 MHz or
higher
 Minimum duration of MIPI D-PHY low power states (tLPX) should be at least 74 ns
 Maximum fabric speed is 150 MHz
 Maximum byte clock frequency is 112 MHz, lower than maximum fabric speed due to heavy logic inside core
modules
 Video VSYNC and HSYNC outputs solely depend on MIPI DSI VSYNC/HSYNC start and end short packets. For
displays that require strict timing, design needs to be modified to have additional control

Lattice Semiconductor MIPI Specifications

General

Brand	Lattice Semiconductor
Model	MIPI
Category	Recording Equipment
Language	English