Lattice Semiconductor MIPI User Manual

MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge Soft IP
User Guide
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FPGA-IPUG-02003-1.2 7
Table 2.1. MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP Pin Function Description (Continued)
Port Name
Direction
Function description
d1_ch1_p_i, d1_ch1_n_i
IO
MIPI D-PHY channel 1 data lane 1. Available only for configurations with two Rx
channels
d2_ ch1_p_i, d2_ ch1_n_i
IO
MIPI D-PHY channel 1 data lane 2. Available only for configurations with two Rx
channels
d3_ ch1_p_i, d3_ ch1_n_i
IO
MIPI D-PHY channel 1 data lane 3. Available only for configurations with two Rx
channels
FPD-Link Interface
clk_ch0_p_o, clk_ch0_n_o
IO
LVDS channel 0 clock lane
d0_ch0_p_o, d0_ch0_n_o
IO
LVDS channel 0 data lane 0
d1_ch0_p_o, d1_ch0_n_o
IO
LVDS channel 0 data lane 1
d2_ ch0_p_o, d2_ ch0_n_o
IO
LVDS channel 0 data lane 2
d3_ ch0_p_o, d3_ ch0_n_o
IO
LVDS channel 0 data lane 3. Available only for configurations with RGB888 data
type
clk_ch1_p_o, clk_ch1_n_o
IO
LVDS channel 1 clock lane
d0_ch1_p_o, d0_ch1_n_o
IO
LVDS channel 1 data lane 0. Available only for configurations with two Tx
channels
d1_ch1_p_o, d1_ch1_n_o
IO
LVDS channel 1 data lane 1. Available only for configurations with two Tx
channels
d2_ ch1_p_o, d2_ ch1_n_o
IO
LVDS channel 1 data lane 2. Available only for configurations with two Tx
channels
d3_ ch1_p_o, d3_ ch1_n_o
IO
LVDS channel 1 data lane 3. Available only for configurations with two Tx
channels and RGB888 data type
Miscellaneous Status Signals
lock_pll_o
O
PLL lock (active high). Available only when miscellaneous status signals option
is enabled
pll_lol_o
O
PLL loss of lock (active high). Available only when miscellaneous status signals
option is enabled
ready_o
O
Indicates reset sequence of DDR components is complete (active high).
Available only when miscellaneous status signals option is enabled
Figure 2.2 shows the single MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP (1:1) block diagram.
DPHY Common Interface
Wrapper
Hard
DPHY
RX Global
Operations
Controller
LP HS
Controller
Capture
Controller
Byte2Pixel
FIFO
PLL
clk_ch0_p_i
clk_ch0_n_i
clk_byte_fr from DPHY
clk_pixel_i
vsync_o
hsync_o
de_o
Pixel data
clk_ref_i
or
clk_byte_fr from
DPHY
d0_ch0_p_i
d0_ch0_n_i
d1_ch0_p_i
d1_ch0_n_i
d2_ch0_p_i
d2_ch0_n_i
d3_ch0_p_i
d3_ch0_n_i
Lane Distr
p_odd_o
LVDS
Wrapper
clk_ch0_p_o
clk_ch0_n_o
d0_ch0_p_o
d0_ch0_n_o
d1_ch0_p_o
d1_ch0_n_o
d2_ch0_p_o
d2_ch0_n_o
d3_ch0_p_o
d3_ch0_n_o
OSC
clk_lp_ctrl
eclk
clk_ref_i
or
clk_byte_fr from
DPHY
clk_ref_i
or
clk_byte_fr from
DPHY
Figure 2.2. Single MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP (1:1) Block Diagram

Lattice Semiconductor MIPI Specifications

General

Brand	Lattice Semiconductor
Model	MIPI
Category	Recording Equipment
Language	English