Lattice Semiconductor MIPI User Manual

MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge Soft IP
User Guide
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20 FPGA-IPUG-02003-1.2
4.4. Generated IP Directory Structure and Files
The directory structure of generated IP files is shown in Figure 4.6.
Figure 4.6. IP Directory Structure
The design flow for the IP created with Clarity Designer uses post-synthesized modules (NGO) of the IP core modules
for synthesis and uses protected models for simulation. The post-synthesized modules are customized when you
configure the IP and created automatically when the IP is generated. The protected models are common to all
configurations.
Table 4.1 provides a list of key files and directories created by Clarity Designer with details on how they are used.
Table 4.1. Files Generated by Clarity Designer
File
Description
<instance_name>.v
Verilog top-level module of MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP used for both
synthesis and simulation.
<instance_name>_*.v
Verilog submodules for simulation. Files that do not have equivalent black box modules are also
used for synthesis.
<instance_name>_*_beh.v
Protected Verilog models for simulation
<instance_name>_*_bb.v
Verilog black box modules for synthesis
<instance_name>_*.ngo
GUI configured and synthesized modules for synthesis
<instance_name>_params.v
Verilog parameters file which contains required compiler directives to successfully configure IP
during synthesis and simulation.
<instance_name>.lpc
Lattice Parameters Configuration file. This file records all the IP configuration options set through
Clarity Designer. It is used by IP generation script to generate configuration-specific IP. It is also
used to reload parameter settings in the IP GUI in Clarity Designer when it is being reconfigured.
<instance_name>_inst.v/vhd
Template for instantiating the generated soft IP top-level in another user-created top module.
All IP files are generated inside \<project_dir> directory (sip3_test2 in Figure 4.6). The \<project_dir> is
<Design Location>\<Design Name>\<Instance Name>, see the Generating IP in Clarity Designer section on
page 17. A separate \<project_dir> is created each time MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP is
created with a different IP instance name.
The \dsi2fpdlink_eval and subdirectories provide files supporting push-button IP evaluation through functional
simulations, design implementation (synthesis, map, place and route) and hardware evaluation.
Inside \dsi2fpdlink_eval is \<instance_name> folder (sip3_test2 in Figure 4.6) which contains protected
behavioral files in \<instance_name>\src\beh_rtl and a pre-built Diamond project in
\<instance_name>\impl\lifmd\<synthesis_tool>. The <instance_name> is the IP instance name specified by
user in Clarity Designer. The simulation part of user evaluation provides testbench and test cases supporting RTL
simulation for Active-HDL simulator under \testbench folder. Pre-built simulation script files are provided in
\<instance_name>\sim\aldec. See the Running Functional Simulation section below for details.
The pll_wrapper model in \<project_dir>\models\lifmd is used for both simulation and implementation.

Lattice Semiconductor MIPI Specifications

General

Brand	Lattice Semiconductor
Model	MIPI
Category	Recording Equipment
Language	English