Lattice Semiconductor MIPI User Manual

MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge Soft IP
User Guide
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6 FPGA-IPUG-02003-1.2
2. Functional Description
The MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP serves as a bridge between a MIPI DSI host and a display
device.
2.1. Top
Figure 2.1 shows the MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP block diagram.
reset_n_i
clk_ref_i
clk_ch0_p_i
clk_ch0_n_i
d0_ch0_p_i
d0_ch0_n_i
d1_ch0_p_i
d1_ch0_n_i
d2_ch0_p_i
d2_ch0_n_i
d3_ch0_p_i
d3_ch0_n_i
clk_ch1_p_i
clk_ch1_n_i
d0_ch1_p_i
d0_ch1_n_i
d1_ch1_p_i
d1_ch1_n_i
d2_ch1_p_i
d2_ch1_n_i
d3_ch1_p_i
d3_ch1_n_i
clk_ch0_p_o
clk_ch0_n_o
d0_ch0_p_o
d0_ch0_n_o
d1_ch0_p_o
d1_ch0_n_o
d2_ch0_p_o
d2_ch0_n_o
d3_ch0_p_o
d3_ch0_n_o
clk_ch1_p_o
clk_ch1_n_o
d0_ch1_p_o
d0_ch1_n_o
d1_ch1_p_o
d1_ch1_n_o
d2_ch1_p_o
d2_ch1_n_o
d3_ch1_p_o
d3_ch1_n_o
lock_pll_o
pll_lol_o
ready_o
Figure 2.1. MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP Block Diagram
Table 2.1. MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP Pin Function Description
Port Name
Direction
Function Description
Clock and Reset
clk_ref_i
I
Reference clock for internal PLL. Available only when MIPI D-PHY clock is non-
continuous
reset_n_i
I
Asynchronous system reset (active low)
MIPI DSI Interface
clk_ch0_p_i, clk_ch0_n_i
IO
MIPI D-PHY channel 0 clock lane
d0_ch0_p_i, d0_ch0_n_i
IO
MIPI D-PHY channel 0 data lane 0
d1_ch0_p_i, d1_ch0_n_i
IO
MIPI D-PHY channel 0 data lane 1
d2_ ch0_p_i, d2_ ch0_n_i
IO
MIPI D-PHY channel 0 data lane 2
d3_ ch0_p_i, d3_ ch0_n_i
IO
MIPI D-PHY channel 0 data lane 3
clk_ch1_p_i, clk_ch1_n_i
IO
MIPI D-PHY channel 1 clock lane
d0_ch1_p_i, d0_ch1_n_i
IO
MIPI D-PHY channel 1 data lane 0. Available only for configurations with two Rx
channels

Lattice Semiconductor MIPI Specifications

General

Brand	Lattice Semiconductor
Model	MIPI
Category	Recording Equipment
Language	English