MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge Soft IP
User Guide
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FPGA-IPUG-02003-1.2 3
Figures
Figure 1.1. MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge System Diagram ............................................................ 4
Figure 2.1. MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP Block Diagram ........................................................... 6
Figure 2.2. Single MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP (1:1) Block Diagram ......................................... 7
Figure 2.3. MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP (1:2, Split) Block Diagram .......................................... 8
Figure 2.4. MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP (2:2) Block Diagram ................................................... 8
Figure 2.5. High-Speed Data Transmission ........................................................................................................................... 9
Figure 2.6. FPD-Link Transmit Interface Timing Diagram (RGB666) ..................................................................................... 9
Figure 2.7. FPD-Link Transmit Interface Timing Diagram (RGB888) ..................................................................................... 9
Figure 2.8. Single MIPI DSI to Dual FPD-Link (Split) Timing Diagram .................................................................................. 10
Figure 2.9. MIPI D-PHY Clock Lane Module State Diagram ................................................................................................ 11
Figure 2.10. MIPI D-PHY Data Lane Module State Diagram ............................................................................................... 11
Figure 4.1. Clarity Designer Window .................................................................................................................................. 16
Figure 4.2. Starting Clarity Designer from Diamond Design Environment ......................................................................... 17
Figure 4.3. Configuring MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP in Clarity Designer ................................ 18
Figure 4.4. Configuration Tab in IP GUI .............................................................................................................................. 18
Figure 4.5. Video Tab in IP GUI ........................................................................................................................................... 19
Figure 4.6. IP Directory Structure ....................................................................................................................................... 20
Figure 4.7. Simulation Environment Block Diagram ........................................................................................................... 23
Figure 4.8. DSI Model Video Data ....................................................................................................................................... 24
Figure 4.9. Regenerating IP in Clarity Designer .................................................................................................................. 26
Tables
Table 1.1. MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP Quick Facts ................................................................. 4
Table 2.1. MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP Pin Function Description ............................................ 6
Table 2.2. Capture Controller Outputs ............................................................................................................................... 11
Table 2.3. Clock Frequency Calculations ............................................................................................................................. 13
Table 2.4. Supported Data Rates for MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP Configurations................. 14
Table 3.1. MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP Parameter Settings ................................................... 15
Table 4.1. Files Generated by Clarity Designer ................................................................................................................... 20
Table 4.2. Testbench Directives .......................................................................................................................................... 21
Table 4.3. Testbench Directives for D-PHY Timing Parameters .......................................................................................... 22
Table 4.4. Testbench Directives for Reference Clock Period .............................................................................................. 22
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