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Lattice Semiconductor MIPI User Manual
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30
Table of Contents
Default Chapter
2
Table of Contents
2
1 Introduction
4
Quick Facts
4
Figure 1.1. MIPI DSI to Openldi/Fpd-Link/Lvds Interface Bridge System Diagram
4
Table 1.1. MIPI DSI to Openldi/Fpd-Link/Lvds Interface Bridge IP Quick Facts
4
Features
5
Conventions
5
Nomenclature
5
Data Ordering and Data Types
5
Signal Names
5
2 Functional Description
6
Top
6
Figure 2.1. MIPI DSI to Openldi/Fpd-Link/Lvds Interface Bridge IP Block Diagram
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Table 2.1. MIPI DSI to Openldi/Fpd-Link/Lvds Interface Bridge IP Pin Function Description
6
Figure 2.2. Single MIPI DSI to Openldi/Fpd-Link/Lvds Interface Bridge IP (1:1) Block Diagram
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Figure 2.3. MIPI DSI to Openldi/Fpd-Link/Lvds Interface Bridge IP (1:2, Split) Block Diagram
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Figure 2.4. MIPI DSI to Openldi/Fpd-Link/Lvds Interface Bridge IP (2:2) Block Diagram
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Figure 2.5. High-Speed Data Transmission
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Figure 2.6. FPD-Link Transmit Interface Timing Diagram (RGB666)
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Figure 2.7. FPD-Link Transmit Interface Timing Diagram (RGB888)
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D-PHY Common Interface Wrapper
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Rx Global Operations Controller
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Figure 2.8. Single MIPI DSI to Dual FPD-Link (Split) Timing Diagram
10
Capture Controller
11
Figure 2.9. MIPI D-PHY Clock Lane Module State Diagram
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Figure 2.10. MIPI D-PHY Data Lane Module State Diagram
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Table 2.2. Capture Controller Outputs
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Byte2Pixel
12
Lane Distribution
12
LVDS Wrapper
12
Reset and Clocking
13
Table 2.3. Clock Frequency Calculations
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Table 2.4. Supported Data Rates for MIPI DSI to Openldi/Fpd-Link/Lvds Interface Bridge IP Configurations
14
3 Parameter Settings
15
Table 3.1. MIPI DSI to Openldi/Fpd-Link/Lvds Interface Bridge IP Parameter Settings
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4 IP Generation and Evaluation
16
Licensing the IP
16
Getting Started
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Figure 4.1. Clarity Designer Window
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Generating IP in Clarity Designer
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Figure 4.2. Starting Clarity Designer from Diamond Design Environment
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Figure 4.3. Configuring MIPI DSI to Openldi/Fpd-Link/Lvds Interface Bridge IP in Clarity Designer
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Figure 4.4. Configuration Tab in IP GUI
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Figure 4.5. Video Tab in IP GUI
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Generated IP Directory Structure and Files
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Figure 4.6. IP Directory Structure
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Table 4.1. Files Generated by Clarity Designer
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Running Functional Simulation
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Table 4.2. Testbench Directives
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Table 4.3. Testbench Directives for D-PHY Timing Parameters
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Table 4.4. Testbench Directives for Reference Clock Period
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Simulation Strategies
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Simulation Environment
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Figure 4.7. Simulation Environment Block Diagram
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Instantiating the IP
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Synthesizing and Implementing the IP
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Figure 4.8. DSI Model Video Data
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Hardware Evaluation
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Enabling Hardware Evaluation in Diamond
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Updating/Regenerating the IP
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Regenerating an IP in Clarity Designer
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Figure 4.9. Regenerating IP in Clarity Designer
26
References
27
Technical Support Assistance
27
Appendix A. Resource Utilization
28
Appendix B. What Is Not Supported
29
Revision History
30
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Lattice Semiconductor MIPI Specifications
General
Brand
Lattice Semiconductor
Model
MIPI
Category
Recording Equipment
Language
English
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