LeCroy 9410

Status Registers 7
Example of status reporting
Summary
STATUS BYTE REGISTER
(STB)
The register structure contains one more register (not shown in
Figure 2). It is the Parallel Poll Enable Register (PRE) which acts
exactly like the Service Request Enable Register (SRE), but it sets
the "ist" bit (not shown in Figure 2), used in the Parallel Poll. The
"ist" bit can also be read with the "*IST?" query.
If an erroneous remote command, e.g. "TRIG_MAKE SINGLE",
is transmitted to the instrument, it rejects the command and sets
the Command Error Register (CMR) to the value 1 (unrecognized
command/query header). The non-zero value of CMR is reported
to bit 5 of the Standard Event Status Register (ESR) which is then
set.
Nothing further happens unless the corresponding bit 5 of the
Standard Event Status Enable Register (ESE) is set (with the com-
mand "*ESE 32"), enabling the fact that bit 5 of ESR is set to be
reported to the summary bit ESB of the Status Byte Register
(STB).
If setting of the ESB summary bit in STB is enabled, again nothing
happens unless further reporting is enabled by setting the corre-
sponding bit in the Service Request Enable Register (with the
command "* SRE 32"). In this case, the generation of a non-zero
value of CMR ripples through to the Master Summary Status bit
(MSS), generating a Service Request (SRQ).
The value of CMR can be read and simultaneously reset to zero at
any time with the command "CMR?". The occurrence of a com-
mand error can also be detected by analyzing the response to
"*ESR?". However, if several types of potential errors must be
surveyed, it is usually much more efficient to enable propagation
of the errors of interest into the STB with the enable registers ESE
and INE.
A command error (CMR) sets bit 5 of ESR:
¯ if bit 5 of ESE is set, ESB of STB is also set.
¯
if bit 5 of SRE is set, MSS/RQS of STB is also set and a
Service Request is generated.
The Status Byte Register is the instrument’s central reporting struc-
ture. The STB is composed of 8 single-bit summary messages (of
which 3 are unused) which reflect the current status of the asso-
ciated data structures implemented in the instrument.
Bit 0 is the summary bit INB of the Internal State Change Register.
It is set if any of the bits of the INR are set, provided that they are
enabled by the corresponding bit of the INE register.
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