Status Registers 7
STANDARD EVENT
STATUS ENABLE
REGISTER (ESE)
Example
SERVICE REQUEST
ENABLE REGISTER (SRE)
The ESE allows one or more events in the Standard Event Status
Register to be reported to the ESB summary bit in the STB.
The Standard Event Enable Register is modified with the com-
mand "*ESE". It is cleared with the command "*ESE 0", or after
power-on. It may be read with the query "*ESE?".
"*ESE 4" sets bit 2 (i.e. binary 4) of the standard event enable
register, enabling query errors to be reported.
The Service Request Enable Register specifies which summary
bit(s) in the Status Byte Register will cause a service request. The
Service Request Enable Register consists of 8 bits. Setting a bit in
the register allows the summary bit located at the same bit position
in the Status Byte Register to generate a service request provided
that the associated event becomes true. Bit 6 (MSS) cannot be set
and is always reported as zero in response to the query "*SRE?".
The Standard Event Enable Register is modified with the com-
mand "*SRE". It is cleared with the command "*SRE 0", or after
power-on. It may be read with the query "*SRE?".
PARALLEL POLL
ENABLE REGISTER (PRE)
The Parallel Poll Enable Register specifies which summary bit(s)
the Status Byte Register will set the "ist" individual local message.
This register is quite similar to the Service Request Enable Register
(SRE), but it is used to set the parallel poll "ist" bit rather than
MSS.
The value of the "ist" may also be read without a Parallel Poll via
the query "*IST?". The response indicates if the "ist" message has
been set or not (values are 1 or 0).
The Parallel Poll Enable Register is modified with the command
"*PRE". It is cleared with the command "*PRE 0", or after pow-
er-on. It may be read with the query "*PRE?". (See Section 3,
page 23, for the GPIB parallel poll procedure.)
Example
"*PRE 5" sets bits 2 and 0 (decimal 4 and 1) of the Parallel Poll
Enable Register.
INTERNAL STATE CHANGE
STATUS REGISTER (INR)
The INR reports the completion of a number of internal opera-
tions. The events tracked by this 16-bit-wide register are listed
with the command "INR?" in Section 5.
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