LeCroy 9410

Status Registers
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STANDARD EVENT
STATUS REGISTER (ESR)
Example
194
Bit 2 is the Value Adapted Bit, indicating that a parameter value
was adapted during a previous command interpretation.
Bit 4 is the Message Available (MAV) bit, indicating that the in-
terface output queue is not empty.
Bit 5 of STB is the summary bit ESB of the Standard Event Status
Register. It is set if any of the bits of the ESR are set, provided that
they are enabled by the corresponding bit of the ESE register.
Bit 6 of the Status Byte Register (STB) is alternatively called the
Master Summary Status bit (MSS) or the Request for Service bit
(RQS) because the STB can be read in two different ways. The
command
"*STB?"
reads and clears the STB in the query mode,
in which case bit 6 of the STB is the MSS bit, indicating if the
instrument has any reason for requesting service. The other way of
reading the STB is the serial poll (see Section 3, page 22, for the
GPIB serial poll procedure). In this case, bit 6 of the STB is the
RQS bit, indicating that the instrument has actually activated the
SRQ line on the GPIB. The serial poll only clears the RQS bit.
Therefore, the MSS bit of the STB (and any other bits which
caused MSS to be set) will stay set after a serial poll. The controller
must reset these bits.
The Status Byte Register may be read via the query "* STB?". The
response represents the binary weighted sum of the register bits.
The register is cleared by
"*STB?",
"ALST?",
"*CLS"
or after
the instrument has been powered up.
The ESR is a 16-bit register reflecting the occurrence of events.
The register bit assignments have been standardized by
IEEE 488.2. Only the lower 8 bits are currently in use.
The Standard Event Status Register may be read via the query
"*ESR?". The response is the binary weighted sum of the register
bits. The register is cleared with an
"*ESR?"
or "ALST?" query, a
"*CLS" command or after power-on.
The response message
"*ESR
160" indicates that a command er-
ror occurred and that the ESR is being read the first time after
power-on. The value 160 can be broken down into 128 (bit 7)
plus 32 (bit 5). See Table 5, page 82, for a description of the
conditions corresponding to the bits set.
The "Power ON" bit appears only on the first
"*ESR?"
query after
power-on because the query clears the register. The type of com-
mand error can be determined by reading the Command Error
Status Register with the query "CMR?". Note that it is not neces-
sary to read (and simultaneously clear) this register in order to
able to set the CMR bit in the ESR on the next command error.