Configuration
Function blocks
Master frequency input (DFIN)
8
8.2
8.2.2
8.2−7
EDSVF9383V EN 7.1−04/2012
In C0425 the output signal can be adapted:
ƒ To the encoder at X9 or
ƒ To the upstream controller with master frequency cascade/master
frequency bus.
Transfer function
Calculating the output signal:
DFIN−OUT[rpm] + f[Hz] @
60
C0425
Example:
The input frequency amounts to 200 kHz, the number of increments
corresponds to 2048 inc/rev. (C0425 = 3).
DFIN−OUT[rpm] + 200000Hz @
60
2048
+ 5859rpm
Signal adaptation
Signal adaptations other than by squaring in C0425 can be achieved by
connecting a function block.
Example:
The function block CONV3 shall convert the speed signal into a quasi analog
signal.
Calculating the output signal at CONV3:
CONV3−OUT[%] + f[Hz] @
0.4
C0425
@
C0950
C0951
Interconnecting function blocks:
CONV3
CONV3-OUTCONV3-IN
C0953
C0952
C0950
C0951
C0425
C0427
DFIN
DFIN-OUT
C0426
X9
fb_dfin_01
Fig. 8.2−6 Digital frequency input (DFIN) with connected converter
Note!
If a master frequency is output to DFOUT−AN−IN or DFOUT−DF
(C0540 = 0 or C0540 = 1) and an incremental encoder is
evaluated via X8, the function block DFIN cannot be used
anymore.
If the input signals at X8 or X9 are output to X10, (C0540 = 4 or
C0540 = 5), this restriction does not exist.
Adjusting the output signal
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