A − 8
6.5 Program Branch Instructions ....................................................................................................6 − 58
6.5.1 Conditional jump, unconditional jump (CJ, SCJ, JMP) ................................................6 − 58
6.5.2 Subroutine call, return (CALL, CALLP, RET)...............................................................6 − 62
6.5.3 Interrupt enable, disable, return (EI, DI, IRET)............................................................6 − 65
6.5.4 Microcomputer program call (SUB, SUBP)..................................................................6 − 68
6.6 Program Switching Instructions ................................................................................................6 − 70
6.6.1 Main ↔ subprogram switching (CHG).........................................................................6 − 70
6.7 Link Refresh Instructions ..........................................................................................................6 − 83
6.7.1 Link refresh (COM) ......................................................................................................6 − 83
6.7.2 Link refresh enable, disable (EI, DI) ............................................................................6 − 85
6.7.3 Partial refresh (SEG) ...................................................................................................6 − 88
7. APPLICATION INSTRUCTIONS..........................................................................................7 − 1 ~ 7 − 148
7.1 Logical Operation Instructions ....................................................................................................7 − 2
7.1.1 16-, 32-bit data logical product (WAND, WANDP, DAND, DANDP) ...............................7 − 3
7.1.2 16-, 32-bit data logical add (WOR, WORP, DOR, DORP) .............................................7 − 8
7.1.3 16-, 32-bit data exclusive logical add (WXOR, WXORP, DXOR, DXORP)..................7 − 12
7.1.4 16, 32-bit data NOT exclusive logical add (WXNR, WXNRP, DXNR, DXNRP) ...........7 − 16
7.1.5 BIN 16-bit data 2’s complement (NEG, NEGP) ...........................................................7 − 20
7.2 Rotation Instructions .................................................................................................................7 − 22
7.2.1 16-bit data right rotation (ROR, RORP, RCR, PCRP)..................................................7 − 23
7.2.2 16-bit data left rotation (ROL, ROLR, RCL, RCLP) .....................................................7 − 25
7.2.3 32-bit data right rotation (DROR, DRORP, DRCR, DRCRP).......................................7 − 27
7.2.4 32-bit data left rotation (DROL, DROLP, DRCL, DRCLP)............................................7 − 29
7.3 Shift Instructions .......................................................................................................................7 − 31
7.3.1 16-bit data n-bit right shift, left shift (SFR, SFRP, SFL, SFLP) ....................................7 − 32
7.3.2 n-bit data 1-bit right shift, left shift (BSFR, BSFRP, BSFL, BSFLP).............................7 − 35
7.3.3 n-word data 1-word right shift, left shift (DSFR, DSFRP, DSFL, DSFLP)....................7 − 37
7.4 Data Processing Instructions....................................................................................................7 − 40
7.4.1 16-bit data search (SER, SERP) .................................................................................7 − 41
7.4.2 16-, 32-bit data bit check (SUM, SUMP, DSUM, DSUMP) ..........................................7 − 43
7.4.3 8 ↔ 256-bit decode, encode (DECO, DECOP, ENCO, ENCOP) ................................7 − 46
7.4.4 7 segment decode (SEG) ............................................................................................7 − 49
7.4.5 Word device bit set, reset (BSET, BSETP, BRST, BRSTP) .........................................7 − 52
7.4.6 16-bit data dissociation, association (DIS, DISP, UNI, UNIP)......................................7 − 54
7.4.7 ASCII code conversion (ASC) .....................................................................................7 − 57
7.5 FIFO Instructions ......................................................................................................................7 − 59
7.5.1 FIFO table write, read (FIFW, FIFWP, FIFR, FIFRP)...................................................7 − 60
7.6 Buffer Memory Access Instructions ..........................................................................................7 − 64
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