Mitsubishi MELSEC-A series - Page 22

2. INSTRUCTIONS
2 − 6
MELSEC-A
(3) Output instructions
Table 2.5 Output instructions
Classi-
fication
Unit
Instruction
Symbol
Symbol Contents of Processing
Execu-
tion Con-
dition
Number of steps
Index
Subset
Applicable CPU Page
1
OUT Device output
3
!
5-14
1
SET Device set *
3
!
5-19
1
RST Device reset *
3
!
5-19
PLS
Generates one-program cycle
pulses on the leading edge of input
signal.
3
!
5-23
PLF
Generates one-program cycle
pulses on the trailing edge of input
signal.
3
!
5-23
OUT

CHK
Device output reverse Valid in I/O
refresh mode
5
Not applicable to An, A3V, A2C,
A3H, A3M, A52G, AnA, A2AS,
QCPU-A (A Mode) and AnU.
5-26
REMARK
Execution Condition marked * in (3) Output instructions:
When the device used is F (annunciator).
When the other device is used.
(4) Shift instructions
Table 2.6 Shift Instructions
Classi-
fication
Unit
Instruction
Symbol
Symbol Contents of Processing
Execu-
tion Con-
dition
Number of steps
Index
Subset
Applicable CPU Page
SFT 3
!
5-28
Shift

SFTP
Shifts device 1 bit
3
!
5-28
(5) Master control instructions
Table 2.7 Master Control Instructions
Classi-
fication Unit
Instruction
Symbol
Symbol Contents of Processing
Execu-
tion Con-
dition
Number of steps
Index
Subset
Applicable CPU Page
MC Master control start 5
!
5-30
Master
control

MCR Master control reset 3
!
5-30
*1: For the number of steps when extension devices are used or when index qualification is performed to
bit devices for AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board, refer to Section 3.8.1.
*2: The
mark in the Index column indicates that index qualification can be performed with the AnA,
A2AS, AnU, QCPU-A (A Mode) and A2USH board only.
*3: The
mark in the Subset column indicates that subset processing can be performed with the A3H,
A3M, AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board only.
*2
*2
*2
*2
*2
*2
*2
*1
*1
*2
*1