Mitsubishi MELSEC-A series - Page 25

2. INSTRUCTIONS
2 − 9
MELSEC-A
Table 2.10 Comparison Operation Instructions
Classi-
fication
Unit
Instruction
Symbol
Symbol Contents of Processing
Execu-
tion Con-
dition
Number of steps
Index
Subset
Applicable CPU Page
LDD= 11
●
!
6-6
ANDD= 11
●
!
6-6
ORD=
Continuity when (S1+1, S1)
= (S2+1, S2)
Non-continuity when (S1+1, S1)
≠ (S2+1, S2)
11
●
!
6-6
LDD<> 11
●
!
6-6
ANDD<> 11
●
!
6-6
ORD<>
Continuity when (S1+1, S1)
≠ (S2+1, S2)
Non-continuity when (S1+1, S1)
= (S2+1, S2)
11
●
!
6-6
LDD> 11
●
!
6-6
ANDD> 11
●
!
6-6
ORD>
Continuity when (S1+1, S1)
> (S2+1, S2)
Non-continuity when (S1+1, S1)
≤ (S2+1, S2)
11
●
!
6-6
LDD<= 11
●
!
6-6
ANDD<= 11
●
!
6-6
ORD<=
Continuity when (S1+1, S1)
≤ (S2+1, S2)
Non-continuity when (S1+1, S1)
> (S2+1, S2)
11
●
!
6-6
LDD< 11
●
!
6-6
ANDD< 11
●
!
6-6
ORD<
Continuity when (S1+1, S1)
< (S2+1, S2)
Non-continuity when (S1+1, S1)
≥ (S2+1, S2)
11
●
!
6-6
LDD>= 11
●
!
6-6
ANDD>= 11
●
!
6-6
32 bit
data
com-
parison
32 bits
ORD>=
Continuity when (S1+1, S1)
≥ (S2+1, S2)
Non-continuity when (S1+1, S1)
< (S2+1, S2)
11
●
!
6-6
*1: For the number of steps when extension devices are used or when index qualification is performed to
bit devices for AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board, refer to Section 3.8.1.
*2: The
mark in the Index column indicates that index qualification can be performed with the AnA,
A2AS, AnU, QCPU-A (A Mode) and A2USH board only.
*3: The
mark in the Subset column indicates that subset processing can be performed with the A3H,
A3M, AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board only.
*1