2. INSTRUCTIONS
2 − 10
MELSEC-A
(2) Arithmetic operation instruction
Table 2.11 Arithmetic Operation Instruction (Continue)
Classi-
fication
Unit
Instruction
Symbol
Symbol Contents of Processing
Execu-
tion Con-
dition
Number
of steps
Index
Subset
Applicable CPU Page
+
5
● ●
!
6-10
+P
(D) + (S) → (D)
5
● ●
!
6-10
+
7
● ●
!
6-10
+P
(S1) + (S2) → (D)
7
● ●
!
6-10
-
5
● ●
!
6-10
-P
(D) - (S) → (D)
5
● ●
!
6-10
-
7
● ●
!
6-10
BIN
16-bit
addition/
subtrac-
tion
16 bits
-P
(S1) - (S2) → (D)
7
● ●
!
6-10
D+
9
● ●
!
6-13
D+P
(D+1, D) + (S+1, S)
→ (D+1, D)
9
● ●
!
6-13
D+
11
● ●
!
6-13
D+P
(S1+1, S1) + (S2+1, S2)
→ (D+1, D)
11
● ●
!
6-13
D-
9
● ●
!
6-13
D-P
(D+1, D) - (S+1, S) → (D+1, D)
9
● ●
!
6-13
D-
11
● ●
!
6-13
BIN
32bit
addition/
subtrac-
tion
32 bits
D-P
(S1+1, S1) - (S2+1, S2)
→ (D+1, D)
11
● ●
!
6-13
∗
7
● ●
!
6-16
∗P
(S1) × (S2) → (D+1, D)
7
● ●
!
6-16
/
7
● ●
!
6-16
BIN
16bit
multipli-
cation/
division
16 bits
/P
(S1) / (S2) → Quotient (D),
Remainder (D+1)
7
● ●
!
6-16
*1: For the number of steps when extension devices are used or when index qualification is performed to
bit devices for AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board, refer to Section 3.8.1.
*2: The
mark in the Index column indicates that index qualification can be performed with the AnA,
A2AS, AnU, QCPU-A (A Mode) and A2USH board only.
*3: The
mark in the Subset column indicates that subset processing can be performed with the A3H,
A3M, AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board only.
*1