Mitsubishi MELSEC-A series - Page 34

2. INSTRUCTIONS
2 − 18
MELSEC-A
(2) Rotation instructions
Table 2.18 Rotation Instructions
Classi-
fication
Unit
Instruction
Symbol
Symbol Contents of Processing
Execu-
tion Con-
dition
Number of steps
Index
Subset
Applicable CPU Page
ROR 3
●
!
7-23
RORP
"n" bit rotation to right
Carry
A0
0
15
3
●
!
7-23
RCR 3
●
!
7-23
Right
ward
rotation
RCRP
Carry
A0
0
15
"n" bit rotation to right
3
●
!
7-23
ROL 3
●
!
7-25
ROLP
Carry
A0
0
15
"n" bit rotation to left
3
●
!
7-25
RCL 3
●
!
7-25
Left
ward
rotation
16 bits
RCLP
0
15
Carry
A0
"n" bit rotation to left
3
●
!
7-25
DROR 3
●
!
7-27
DRORP
0
15
Carry
0 15
A1 A0
"n" bit rotation to right
3
●
!
7-27
DRCR 3
●
!
7-27
Right
ward
rotation
DRCRP
A1 A0
0
15
Carry
0 15
"n" bit rotation to right
3
●
!
7-27
DROL 3
●
!
7-29
DROLP
A1 A0
0
15
Carry
0 15
"n" bit rotation to left
3
●
!
7-29
DRCL 3
●
!
7-29
Left
ward
rotation
32 bits
DRCLP
0
15
Carry
0 15
A1
A0
"n" bit rotation to left
3
●
!
7-29
*1: For the number of steps when extension devices are used or when index qualification is performed to
bit devices for AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board, refer to Section 3.8.1.
*2: The
mark in the Index column indicates that index qualification can be performed with the AnA,
A2AS, AnU, QCPU-A (A Mode) and A2USH board only.
*3: The
mark in the Subset column indicates that subset processing can be performed with the A3H,
A3M, AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board only.
*1