2. INSTRUCTIONS
2 − 20
MELSEC-A
(4) Data processing instructions
Table 2.20 Date Processing Instructions
Classi-
fication
Unit
Instruction
Symbol
Symbol Contents of Processing
Execu-
tion Con-
dition
Number
of steps
Index
Subset
Applicable CPU Page
SER
9
●
!
7-41
Date
search
SERP
9
●
!
7-41
SUM
3
●
!
7-43
16 bits
SUMP
3
●
!
7-43
DSUM
3
●
!
7-43
Bit
check
32 bits
DSUMP
3
●
!
7-43
DECO
9
●
!
7-46
DECOP
9
●
!
7-46
ENCO
9
●
!
7-46
Decode
Encode
2n bits
ENCOP
9
●
!
7-46
7.seg-
ment
decode
SEG
7
●
Not applicable to A3V. 7-49
BSET
7
●
!
7-52
BSETP
7
●
!
7-52
BRST
7
●
!
7-52
Bit set
reset
BRSTP
9
●
!
7-52
DIS
9
●
!
7-54
DISP
9
●
!
7-54
UNI
9
●
!
7-54
Accocia
-tion
Dissoci-
ation
16 bits
UNIP
9
●
!
7-54
ASCII
conver-
sion
ASC
Converts alphanumeric characters
into ASCII codes and stores into 4
points beginning with the
devices, D.
13
●
!
7-57
*1: For the number of steps when extension devices are used or when index qualification is performed to
bit devices for AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board, refer to Section 3.8.1.
*2: The
mark in the Index column indicates that index qualification can be performed with the AnA,
A2AS, AnU, QCPU-A (A Mode) and A2USH board only.
*3: The
mark in the Subset column indicates that subset processing can be performed with the A3H,
A3M, AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board only.
Decode from 256 to 8
2
n
bits
Encode
(S)
(D)
n
Decode from 8 to 256
(D)
(S)
n
2
n
bits
Decode
*3
*1
*3
A0 : Quantity of 1
0
15
(S)
A0 : Quantity of 1
(S)
(S+1)
*3
A0 : Coinciding number
A1 : Coinciding quantity
(S2)
n
(S1)
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