Mostek z80 - Target System Configuration

2-6
2.6 TARGET SYSTEM CONFIGURATION
AIM:::rZ80AE is designed to be as independent of the Target configuration as
practical; however, there are some restrictions on the Target system.
1. '!he Target PHI clock must be ill the rafl3e of 500kHz to 4 MHz.
2. '!he Target system must be able to supply the extra specified 5 volt
power to the buffer box, and the ground bus to the CPU socket must be
substantial.
3. 'Ihe signals RESET, BUSRQ, WAIT cannot be in the active state during
ini tialization.
4. The Target Data bus must be tristate except when MREQ OR IORQ are ac~
tive.
5. !Vbst output signals from the Buffer module will only drive 1.4 rnA and
still meet the 0.4 volt output low voltage specification. These signals
will still drive 1.8 I~ at an output low voltage of 0.5 volt.